TCAN4550EVM: TCAN4550 MRAM Tx Buffer FIFO/Queue

Hello Nomura-san,

You may need to modify the TCAN4x5x_MRAM_Configure() function in the TCAN4550.c file to remove the line setting it to Queue mode by setting the TFQM bit.  By default the device uses FIFO mode.

    // TX Buffer
    MRAMValue = MRAMConfig->TxBufferNumElements;
    if (MRAMValue > 32)
        MRAMValue = 32;


    registerValue = 0;
    if (MRAMValue > 0)
    {
        registerValue = ((uint32_t)(MRAMValue) << 24) | ((uint32_t)startAddress);
        registerValue |= REG_BITS_MCAN_TXBC_TFQM;               // Sets TFQM to 1 (Queue mode), and sets all registers to be generic non-dedicated buffers.
    }
    startAddress += (((uint32_t)TCAN4x5x_MCAN_TXRXESC_DataByteValue((uint8_t)MRAMConfig->TxBufferElementSize) + 8) * (uint16_t)MRAMValue);
    AHB_WRITE_32(REG_MCAN_TXBC, registerValue);

Unfortunately the Protocol Status Register resets after it is read and the returned value you shared doesn't appear to be from the first read after the error occurred.  Both the DLEC and LEC values are "7" which means no change since previous read. 

Generally speaking protocol errors in the data phase come from different bit timing configurations between the nodes on the bus that cause sampling errors.  With CAN FD using Bit Rate Switching, the switch to the faster data bit rate occurs at the sample point in the BRS bit in the message header.  Therefore all devices need to have the same sample point and bit timing configuration so the switch to the faster bit rate occurs on all devices simultaneously.   If any are different, then the devices may sample the bit at different times causing errors.

You may want to verify the data bit timing settings are the same for all nodes on your bus.

Regards,

Jonathan

Hello Jonathan,

Thank you for your answer.

After disabling the code as you suggested, I confirmed successful transmission.

Regards,

Nomura