• State
  • Locked Locked
  • Replies 4 replies
  • Subscribers 33 subscribers
  • Views 971 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

XIO2000A Memory-Mapped TI Proprietary Register Space

Alexander2000a
Prodigy 20 points
Other Parts Discussed in Thread: XIO2000A, XIO2001

Dear Community:

I need to access Memory-Mapped TI Proprietary Register Space of XIO2000A. How do I find the base address where those registers are mapped to?

lspci -vvv gives me:


PCI Device behind the bridge:

cat /proc/iomem gives me:

My OS is Linux with kernel version 2.6.34-12.

Thank you for your reply.

Alexander

  • 0
    TI__Guru* 76130 points

    Hello Alexander,

    We are reviewing your issue and will repply soon.

    Regards.

  • 0
    TI__Guru* 76130 points

    Hello Alexander,

    TI does not publish the contents/location of these registers. They should be left alone as changing any of these registers can/will cause unexpected operation of the device.

    Also, please note that XIO2000A is not recommended for new designs and it has been superseded by the XIO2001.

    Regards.

  • 0 in reply to Elias Villegas M.
    Prodigy 20 points

    Elias:

    Thank you for your reply.

    > Also, please note that XIO2000A is not recommended for new designs and it has been superseded by the XIO2001.

    Unfortunately, I cannot switch to another bridge and need to configure this one.

    >TI does not publish the contents/location of these registers. They should be left alone as changing any of these registers can/will cause unexpected operation of the device.

    I just need those features described in "3.5.2 PCI Isochronous Windows" and "3.5.3 PCI Express Extended VC with VC Arbitration". How can I do that without Memory-Mapped TI Proprietary Register Space? I already can access PCIe memory mapped registers.

    Happy New Year, Elias.

    Regards.

    Alexander

  • 0 in reply to Alexander2000a
    TI__Intellectual 1710 points

    The Base Address Register for the registers in section 3.5.2 and 3.5.3 are mapped through the Device Control Memory Register at PCI offset 10h. Refer to table 6-1 for the memory map for all the Device Control Memory registers.