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CPRI Rate 7 Supproting

Jin Kyung Han
Expert 1520 points
Other Parts Discussed in Thread: TLK10002

Hello

I am going to use the TLK10002 for CPRI which is applied for RRH(Remote Radio Head).

Anyone who knows about Rate 7 standard of CPRI? Doest the TLK10002 support CPRI Rate7?

If anyone who have detail information about the CPRI Rate 7, please let me know how to apply the TLK10002 for CPRI Rate7

Thanks 

  • 0
    TI__Expert 7850 points

    Hello,

    TLK10002 is capable of supporting all CPRI data rates from 614Mbps to 9.8Gbps.  Please see pages 16 to 18 of the TLK10002 data sheet for all possible line rates that the device can support.

    Thanks,

    Atul Patel

  • 0 in reply to Atul Patel
    Expert 1520 points

    Hello

    I checked the Version of CPRI on the data sheet of TLK10002 which can support all CPRI Rate.

    THe below is our target configuration for sending CPRI data to the Rx. RRH is ready to 10G coded 8B/10B and the data goes to FPGA which will fragment 1 x 4 = 2.5G respectively. From this, I want to know the fragment format to meet CPRI data format, what the format should use for the CPRI which Rx expect decoding CPRI through Serdes.

    RRH ==> 1x4 fragmentation(FPGA) ==> 4x1 Mux(TLK10002) ==> 1x4 DEMUX(TLK10002) ==> BB(Base Station)

    Thanks

    JK Han

  • 0 in reply to Jin Kyung Han
    TI__Expert 7850 points

    JK,

    Can you please send me your email address so that I can send you files needed to help answer your question on data formating between the serdes and FPGA.

    thanks,

    Atul Patel

    atulp@ti.com

  • 0 in reply to Atul Patel
    Expert 1520 points

    Atul

    I email you and waiting for the data.

    Thanks

  • 0 in reply to Atul Patel
    Expert 1520 points

    Hello

    I have questions more on the TLK10002 applying for CPRI. Our Data speed is 10G.  

    1. Is is support Auto-negotiation between Tx and Rx range from 1.2288G ~9.8304G? If it can support, How to implemnt the Auto negotiation.

         If the Lane devided to 4, How to align the 49 Charaters for 4 goup?

     
           ex) k28.5 -> lane ?
             D30.5 -> lane ?  ----4 times repeatition in period. 
             D23.6 -> lane ?
             D3.1   -> lane ?
             D7.2   -> lane ?
             D11.3 -> lane ?
             D15.4 -> lane ?
             D19.5 -> lane ?
             D20.0 -> lane ?
             D30.2 -> lane ?
             D27.7 -> lane ?
             D21.1 -> lane ?
             D25.2 -> lane ?  ----4 times repeatition in period

    2. For implementing 1.2288G ~ 9.8304G , Clock for TLK is only using  Reference clock을 122.88MHZ  or 153.6MHZ ? 

    3. Can we have the the source code of XILINX  on the TLK EVM B'D?

    Thanks

    lawrence.han@wtmec.com

     


     

  • 0 in reply to Jin Kyung Han
    TI__Expert 7850 points

    Lawrence,

    Here are some answers to your questions:

    1. Auto Negotiation is not supported. The FPGA code data that I sent should provide information on the link training implementation.

    2. TLK10002 can support a wide range of reference clocks please see pages 17 and 18 of the data sheet.  We give examples at 122.88MHz and 153.6MHz as they are common CPRI clocks.

    3. FPGA  data file has been sent in a separate email.

    Thanks,

    Atul