I just got a customer question on the SN65LV1023A/SN65LV1224B
1) Data Sheet for SN65LV1023A/SN65LV1224B, Feb. 2009. In this data sheet is the pinout of the deserializer chip missing.
2) Page 10 of the above data sheet:Deserializer Timing Requirements for REFCLK:
We receive data with 310MHz = 620Mbps. What is the frequency for REFCLK? Do we need 63MHz +-100ppm? Or can we use a clock of 63MHz with +-5% (like defined in the National data sheet)?
The device we have to interface uses 310MHz for the chip internal data serializer, which gives us a data rate of 620Mbps. The data stream has 1 stop, 1 start and 10 data bits. Andnow I wonder, what frequency REFCLK should get? Please give me detailed information about this input clock signal. I do not understand, why it is needed. The data sheet defines +-100ppm. And I wonder: 100ppm of what?
3.) It is easy for me to send a constant sync pattern. If i would send $3F (all 10 bits high) as Sync pattern, the receiver would immediately lock after 4 cycles? Is this true?
According to the datasheet the deserializer needs at least 4 consecutive cycles of data to go into lock. Is there anything else he needs to be aware of?4) If the sending device shows some temperature drift, some voltage drift, on the data stream, does the SN65LV1224B follow this drift or what will happen during decoding?
We want to / have to build a robust interface, which, when locked, stays locked for weeks of continuous operation.
