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ADS131M04EVM: ADCs does not remain in sync after some period of sync command is sent

shraddha naik
Intellectual 290 points
Part Number: ADS131M04EVM
Other Parts Discussed in Thread: ADS131M04

Tool/software:

Dear team,

I have connected 2 ADS131 evm board (with external supply) to MCU over same SPI lines(MISO, MOSI, SCLK). DRDY & CS for both ADCs connected to separate GPIOs.

OSR I have kept 512 (8Ksps), 

Once i toggled the Sync pin, both ADCs are in sync, but after some period both ADCs are slowly coming out of sync. I am monitoring DRDY signal of both adc & below i have attached the screenshot once sync is toggled & after 1minute of sync.

1. Once sync is toggled

2. After a minute, shift between both DRDY is ~4.5us.

If this behaviour is common, then at what rate we need to sync the device?

Also I have seen once sync is done, the next response which i get on both adc is varying sometimes. This i checked on multiple trials of sending the sync signal. RESET bit & REG_MAP bit sets in STATUS register, even if ADC is not resetted or reset signal is not given.

Regards,

Shraddha

  • 0
    TI__Mastermind 45895 points

    Hi shraddha naik,

    Are you using the same clock from the same oscillator or each EVM uses its own oscillator on the EVM?

    BR,

    Dale

  • 0 in reply to Dale Li
    Intellectual 290 points

    Hi Dale,

    Each evm uses its own oscillator on the evm.

    Regards,

    shraddha

  • 0 in reply to shraddha naik
    TI__Mastermind 45895 points

    Hi shraddha naik,

    In order to synchronize multiple ADS131M04 ADCs, the same oscillator should be used or shared between the ADCs/EVMs. You can remove the jumper on JP6 on one of ADS131M04EVMs, then use a wire to connect the clock from another EVM to pin 2/4/6 of this EVM for sharing the same clock.

    BR,

    Dale

  • 0 in reply to Dale Li
    Intellectual 290 points

    HI Dale,

    In our application, we use separate oscillator for both ADCs.

    shraddha naik said:
    Also I have seen once sync is done, the next response which i get on both adc is varying sometimes. This i checked on multiple trials of sending the sync signal. RESET bit & REG_MAP bit sets in STATUS register, even if ADC is not resetted or reset signal is not given.

    Also, can you reply to this.

    Regards,

    shraddha

  • 0 in reply to shraddha naik
    TI__Mastermind 45895 points

    Hi shraddha,

    Also I have seen once sync is done, the next response which i get on both adc is varying sometimes. This i checked on multiple trials of sending the sync signal.

    When a negative SYNC pulse is applied on the SYNC/RESET pin, the device internally compares the leading negative edge of the pulse to its internal clock that tracks the data rate. The internal data rate clock has timing equivalent to the DRDY pin if configured to assert with a phase calibration setting of 0b. If the negative edge on SYNC/RESET aligns with the internal data rate clock, the device is determined to be synchronized and therefore no action is taken. If there is misalignment, the digital filters on the device are reset to be synchronized with the SYNC/RESET pulse. When two separated oscillators are used for both ADCs, definitely it is possible they could have a different next response (duration time from the moment the SYNC is applied), but the ADCs should be  synchronized, you can check the falling edge of /DRDY of both ADCs.

    RESET bit & REG_MAP bit sets in STATUS register, even if ADC is not reseted or reset signal is not given.

    The SYNC/RESET pin is a dual-function pin that allows synchronization of conversions to an external event and allows for a hardware device reset. Provide a negative pulse on the SYNC/RESET pin with a duration less than tw(RSL) but greater than a CLKIN period to trigger synchronization. A negative pulse on the SYNC/RESET pin with a duration greater than tw(RSL) will lead to a reset and set the RESET bit in the STATUS register. The REG_MAP bit in the STATUS register is set to flag the host if the register map CRC changes, including changes resulting from register writes.

    but after some period both ADCs are slowly coming out of sync.

    When you use separated oscillators for both ADCs, the oscillators can shift differently and causes the host and device to become out of synchronization, so a periodic synchronization to realign the data capture between both ADCs is needed. It would be better to use the same clock source.

    BR,

    Dale

  • 0 in reply to Dale Li
    Intellectual 290 points

    Hi Dale,

    Thanks for the clarification.

    Dale Li said:
    The SYNC/RESET pin is a dual-function pin that allows synchronization of conversions to an external event and allows for a hardware device reset. Provide a negative pulse on the SYNC/RESET pin with a duration less than tw(RSL) but greater than a CLKIN period to trigger synchronization. A negative pulse on the SYNC/RESET pin with a duration greater than tw(RSL) will lead to a reset and set the RESET bit in the STATUS register. The REG_MAP bit in the STATUS register is set to flag the host if the register map CRC changes, including changes resulting from register writes.

    But, for this topic, we made sure that sync/reset pin is toggled for ~2us to sync both ADCs. 

    STATUS Reg response: 0x450F --> 0100 0101 0000 1111 -->10th bit Reset status, 14th bit Resync status

    Reset status bit is set for sync command too. Can you please clarify on this.

    Regards,

    shraddha

  • 0 in reply to shraddha naik
    TI__Mastermind 45895 points

    Hi shraddha,

    Can you please provide the timing including SPI bus and /SYNC and /DRDY? the timing of the frames before and after /SYNC captured with logic analyzer would be good.

    BR,

    Dale 

  • 0 in reply to Dale Li
    Intellectual 290 points

    Hi Dale,

    I have attached the SPI bus data along with DRDY & Sync signals before & after sync.

    Before sync

    Sync pin toggled for 2.5us

    time duration till 1st DRDY interrupt comes after sync is 123us

    Device 1 data after sync. Here 1st 16bit response STATUS Reg: 0x450F 

    Same response on device 2 as well

    Regards,

    Shraddha

  • 0 in reply to shraddha naik
    TI__Guru 52576 points

    Hi shraddha naik,

    Dale is out of the office right now so I will help you until he returns

    Are you using 24-bit frames? It is confusing to me because all of your data is sent as one group of two bytes followed by another byte. Why aren't you just sending all 3 bytes at once?

    And why not bring CS high at the end of each frame to ensure the device doesn't get out of sync? Any glitch on the SCLK pin will be treated as a valid input by the ADC, which throws off your communication.

    -Bryan

  • 0 in reply to Bryan Lizon86
    Intellectual 290 points

    Hi, Bryan,

    Yes i am using 24bit frame, & since my MCU does not support 24bit, i had choice of sending 8bit 3times or 16+8bit. I feel the later option saves the data transmission time.

    Bryan Lizon86 said:
    And why not bring CS high at the end of each frame to ensure the device doesn't get out of sync?

    Its the TI library code i am using to read ADC channel data, where CS pin is made low & then it reads all 4 channel data before CS pin made high. CS pin is not made high after each frame.

    Bryan Lizon86 said:

    Any glitch on the SCLK pin will be treated as a valid input by the ADC, which throws off your communication.

    There is no glitch i have seen on SCLK or CS pin.

    Regards,

    Shraddha

  • 0 in reply to Bryan Lizon86
    Intellectual 290 points

    Hi, Bryan,

    Yes i am using 24bit frame, & since my MCU does not support 24bit, i had choice of sending 8bit 3times or 16+8bit. I feel the later option saves the data transmission time.

    Bryan Lizon86 said:
    And why not bring CS high at the end of each frame to ensure the device doesn't get out of sync?

    Its the TI library code i am using to read ADC channel data, where CS pin is made low & then it reads all 4 channel data before CS pin made high. CS pin is not made high after each frame.

    Bryan Lizon86 said:

    Any glitch on the SCLK pin will be treated as a valid input by the ADC, which throws off your communication.

    There is no glitch i have seen on SCLK or CS pin.

    Regards,

    Shraddha

  • +1 in reply to shraddha naik
    TI__Mastermind 45895 points

    Hi shraddha,

    Thanks for your patience. I checked the timing you shared and all information you provided. 

    You had a concern about  "STATUS Reg response: 0x450F --> 0100 0101 0000 1111 -->10th bit Reset status, 14th bit Resync status"

    Reset bit: The RESET status bit in the STATUS register is always 1b by default after the ADC is powered up, you can see this bit is set to "1" when you read data in each frame, so the response from ADS131M04 is correct. You can write 0b to the RESET bit in the MODE register to clear the RESET status bit in the STATUS register before you read the STATUS register from the ADC.

    Resync bit: The F_RESYNC bit in the STAATUS register is a ADC resynchronization indicator and it lets you know if a resynchronization has occurred, so the response from the ADS131M04 ADC is correct.

    You also mentioned "where CS pin is made low & then it reads all 4 channel data before CS pin made high. CS pin is not made high after each frame." please note that toggling /CS for each frame is recommended, otherwise you have to make sure the right number of bytes/SCLKs are sent to the ADC when you communicate with the ADC.

    BR,

    Dale