AM26LS32A: -

Part Number: AM26LS32A

Tool/software:

Hello,

I’m using a TI RS422 Receiver, AM26LS32AIDR, and need to bias the input resistors such that the output will always be low during the failsafe condition. I never want to see a high output during the failsafe condition. I’ve read the following TI app note. If I understand this correctly, I need to have |Vb| > |Va| and have sufficient differential voltage to exceed VIT of the receiver.

https://www.ti.com/lit/an/slyt324/slyt324.pdf 

For the following set of resistors (please refer to the attached schematic)

R1= 560 Ohm

R2= 620 Ohm

R3(termination)= 100 Ohm

 Doing the math I get

 Vb= 2.58V

Va= 2.19V

Vb-Va= 0.39V (which is outside of the +/-200mV undefined region)

I’ve read somewhere that it is preferable to have R1 and R2 be the same value to keep the line balanced, but the problem is that I won’t be able to achieve |Vb| > |Va|.

 Do you think I’ve covered all the bases here to guarantee a low output value in the failsafe mode?

 Thank you very much for your support

Ray

AM26LS32AIDR_.docx

  • Hi Ray,

    The device itself has some internal resistances that you could include in your simulation if you'd like. Figure 7-5. The external resistors are so much smaller than the internal ones that I would just ignore them. 

    Vb-Va= 0.39V (which is outside of the +/-200mV undefined region)
    but the problem is that I won’t be able to achieve |Vb| > |Va|.

    You do meet the requirement.

    Using your values, Vb-Va = -390mV which is less than -200mV (Vth-) so you have around 190mV of noise margin if we use the min value here.

    With Hysteresis the value becomes 240mV. In most systems this would be enough to provide a fail safe that ensures 1Y outputs a logic low during the open condition.

    -Bobby

  • Hi Bobby,

    Thank you so much for your prompt response. A few follow-up questions:

    (1) I see the internal resistance in the datasheet is stated to be 15K Ohm typical. Does that sound right to you? Is that 15K across the A and B inputs I suppose?

    (2) I’m a bit confused by what you said about not including the external resistors in the simulation, but wouldn’t that not give me the offset that I need?

    (I’m not simulating the circuit, just calculating the biasing resistor values).

    (3) It sounds like with these resistor values I’ll able to ensure a logic low output during the open condition but what about the concept that these biasing resistors are not equal in value? Would that create any unbalanced issues?

     

    Regards,

    Ray

  • (1) I see the internal resistance in the datasheet is stated to be 15K Ohm typical. Does that sound right to you? Is that 15K across the A and B inputs I suppose?

    That's the defined leakage across the common mode range. You can choose to model this as a worst case scenario.

    (2) I’m a bit confused by what you said about not including the external resistors in the simulation, but wouldn’t that not give me the offset that I need?

    The opposite, not including the internal registers (I'm saying ignore the internal leakage). 560 ohm << 100k ohm the eq resistance is basically 560 ohms anyways so 100k is not relevant. 

    (I’m not simulating the circuit, just calculating the biasing resistor values).

    Sorry, I assumed your circuit was taken from a simulation tool.

    Example below where using 12k internal with worst case condition of GND shift doesn't do much to the biasing voltage across 100 ohms. This case You still have a fair bit of margin against noise. 

    Below is your base case with a VoC of 2.38V

    (3) It sounds like with these resistor values I’ll able to ensure a logic low output during the open condition but what about the concept that these biasing resistors are not equal in value? Would that create any unbalanced issues?

    You're technically generating a much stronger Biasing voltage than someone who does not use the external biasing so the VoC is actually going to be more stable. If you're worried about this, then using split termination with a filtering cap will provide much more stable VoC for the AC frequency. You could also add in a common mode choke to further stablize the VoC. Then lastly to ensure VoC delta isn;t emitting too much, use a shielded twisted pair cable. Though, I think you may be over thinking this unless you absolutely need to pass some sort of EMI compliance. 

    -Bobby

  • Hi Bobby,

    Thank you so much. You've been a great help. It looks like with the selected resistors I have plenty of margin to meet the requirement of logic low on the output during the open condition. I'll go ahead and close this case now.

    Take care.

    Ray