Tool/software:
Hello,
I’m using a TI RS422 Receiver, AM26LS32AIDR, and need to bias the input resistors such that the output will always be low during the failsafe condition. I never want to see a high output during the failsafe condition. I’ve read the following TI app note. If I understand this correctly, I need to have |Vb| > |Va| and have sufficient differential voltage to exceed VIT of the receiver.
https://www.ti.com/lit/an/slyt324/slyt324.pdf
For the following set of resistors (please refer to the attached schematic)
R1= 560 Ohm
R2= 620 Ohm
R3(termination)= 100 Ohm
Doing the math I get
Vb= 2.58V
Va= 2.19V
Vb-Va= 0.39V (which is outside of the +/-200mV undefined region)
I’ve read somewhere that it is preferable to have R1 and R2 be the same value to keep the line balanced, but the problem is that I won’t be able to achieve |Vb| > |Va|.
Do you think I’ve covered all the bases here to guarantee a low output value in the failsafe mode?
Thank you very much for your support
Ray