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TCAN1145-Q1: Inquiry Regarding TCAN1145 Selective Wakeup Issue

JAEHYEON LEE
Prodigy 10 points
Part Number: TCAN1145-Q1

Tool/software:

We are currently using the TCAN1145 device in our controller development, specifically utilizing the Selective Wakeup feature. However, we have encountered an issue where the device occasionally fails to wake up even when a wakeup CAN message is sent.

Upon checking the fault registers, we observed the following:

  • INT_1: FRAM_OVF, CANSLNT, CANTO bits are set
  • INT_3: SWERR bit is set

We have two questions regarding this situation:

Q1. What could be the possible causes for these fault conditions (FRAM_OVF, CANSLNT, CANTO, SWERR) occurring simultaneously and preventing wakeup?

Q2. In such a fault state, what steps should be taken to recover the device and return it to normal operation?
For example:

  • Clearing INT_1, INT_2, INT_3, and CAN_BUS registers
  • Setting the SWCFG bit to 1 in the SW_CONFIG_4 register

We would appreciate your guidance on the correct recovery procedure and any preventive measures we should consider.

  • +1
    TI__Mastermind 28530 points

    Hi Jaehyeon,

    Failure to wakeup here is because of the frame overflow bit set. This bit is set because of receiving too many error frames that exceeds the error counter threshold in 0x46 register. Frame overflow will also set SWERR bit which will disable the selective wakeup. The CANSLNT and CANTO are set because the bus being idle for a certain period of time, and note that once those interrupts are set, they won't be cleared automatically so you need to clear those bits manually.

    In such a fault case, you can clear all the interrupt registers, then set SW_EN to 1. SWCFG bit should still remain 1 unless you change any selective wakeup configuration registers, which seems not the case here. I also recommend during the initialization, or every time you want to enter sleep mode with selective wakeup enabled, make sure to clear those interrupt registers before setting SW_EN to 1.

    Please let me know if this doesn't solve your issue.

    Regards,

    Sean

  • 0 in reply to Sean Guo
    Prodigy 10 points 
    When clearing the INT register, should I write 0 or 0xFF?
  • +1 in reply to JAEHYEON LEE
    TI__Guru 74292 points

    Jaehyeon,

    Please write 0xFF, the bit is cleared when 1 is written to it.

    Regards,

    Eric Hackett 

  • 0 in reply to Eric Hackett
    Prodigy 10 points

    Last question. When powered on, the PWRON bit is set to 1 in the INT_2 register, right? Does this bit cause a global error? In some cases, INT_GLO has a value of 0xA0 but when INT_2 is checked, it is 0x40.

  • +1 in reply to JAEHYEON LEE
    TI__Mastermind 28530 points

    Hi Jaehyeon,

    Yes, any interrupt will set the global interrupt. 0xA0 means GLOBALERR and INT_2 are set, and a PWRON set in INT_2 register is 0x40.

    Regards,

    Sean