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DS250DF230EVM: PRBS Configuration at 6.375Gbps

Part Number: DS250DF230EVM
Other Parts Discussed in Thread: DS250DF230,

Tool/software:

Dump.cfg

Hi Team

I have the DS250DF230 EVM and trying to make PRBS pattern

I am having problems with the setup and couldn't generate test pattern at 6.375Gbps

I saw in the E2E forum that i need to provide the required bit rate at the input or subset of it for the CDR to lock

So i provides 6.375G/16=398.43MHz input as sine wave and also tried with square wave but without success

I added the register dump for your investigation

Can you help me to figure out the correct setup and register setting for having PRBS pattern at 6.375Gbps

Can you share the correct register configuration?

Regards,

Roey

  • Hi Roey,

    In order to manually set the data rate, the steps in Section 7.7 of the device's programming guide must be implemented to configure registers 0x60 - 0x63. For a data rate of 6.375 Gbps, the following configuration should be used.

    If using a 25 MHz reference clock:

    Register              Value

    0x60                    0xC0

    0x61                    0xBF

    0x62                    0xC0

    0x63                    0xBF          

    If using a 30.72 MHz reference clock:

    Register              Value

    0x60                     0xE1

    0x61                     0xB3

    0x62                     0xE1

    0x63                     0xB3         

    You will also need to force the output divider. For your desired data rate, this is done by setting register 0x18[6:4] to 010 and bit 2 of 0x09 to 1. Also, very low frequency sub-rate inputs can result in additional jitter. For this reason, try using a 25.5/16 = 1.59375 GHz input. 

    Best regards,

    Greg

     

  • Hi Greg
    Thanks a lot for the fast reply
    Why do you mention sub rate of 25.5/16 if my required output is 6.375Gbps?
    Regards
    Roey
  • Hi Roey,

    The 25.5/16 = 1.59375 GHz input is also a sub-rate of 6.375 Gbps. As your desired output data rate is a div-4 sub-rate of 25.5 Gbps, I noted the input frequency as 25.5/16, but this is also equal to 6.375/4. The higher frequency input should decrease jitter in your implementation. 

    Best regards.

    Greg

  • Hi Greg

    I modified the suggested registers as you requested but i still couldnt reach PRBS at 6.375Gbps

    I injected 398.43MHz because i cannot generate 1.59375GHz i don't care currently about the Jitter

    In the real system my input is 6.375Gbps and it needs to be retimed 

    Dump file is attached

     Dump_updated.cfg

    Can you suggest a complete register configuration that generates the 6.375Gbps PRBS based on the 398.43MHz input clock?

    Regards,

    Roey

  • One more question, to which configuration user guide do you refer? I am familiar with the SNLU238A and i dont see there section 7.7

  • Hi Roey,

    Here is a configuration that will generate 6.375Gbps PRBS for a 398.4375 MHz. For the EVM set-up, make sure J3 is configured for a 25 MHz CAL_CLK. 

    Register                 Write

    0x60                       0xC0

    0x61                       0xBF

    0x62                       0xC0

    0x63                       0xBF

    0x64                       0xFF

    0x09                       0x04

    0x18                       0x20

    0x0A                       0x0C

    0x0A                       0x00

    Following this configuration, your board should have CDR lock at Channel 0 and can output the PRBS signal you set. If you are looping the TX back to the DS250DF230EVM to use the board's PRBS checker, you will need to complete the same configuration as above for the RX channel you use. Please let me know if this setup works. 

    Also, I was referencing the Programming Guide for the device, which can be accessed by following the "Request more information" link on the DS250DF230 device product page.

    Best regards,

    Greg