Tool/software:
How to config ETH PHY chip to achieve better performance test in EMC BCI Test
We are developing an industrial product, which integrates DP83TC813R-Q1. The product uses RMII interface and works as slave, we used all default configuration. In normal operation, the data update rate is 600Hz, total data in 1s is <0.2Mbps, far below 100Mbps. In normal mode without EMI, I can always read SQI=7 and no data loss. During BCI test, I observed significant variation of SQI, even equal to 1 for a dozen of seconds, but link status is always link up. During 10mins BCI test (1MHz-200MHz), especially in high-frequency (50-200MHz), I can observed a few data loss, in HW design, we have followed most of the guidance from TI, I am wondering is there any SW configuration in registers, which can help improve the performance in BCI test. I read a tech note, SNLA389, it is said that x085A/x086A can improve RF immunity performance, I can’t find them in official datasheet, could you pls provide more details or any other recommendation?
