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SN65HVD63: Single power supply usage

Matthew G
Prodigy 10 points

Part Number: SN65HVD63

Tool/software:

Hi,

As long as we use a compatible voltage range for both power supply inputs and the recommended decoupling capacitance and layout guidelines, would there be any issues if we powered both VL and VCC using the same supply?

Thank you

  • +1
    Intellectual 330 points

    99% Yes problem. If the supply rail is noisy, it can impact the performance of the device's integrated active bandpass filter, which is designed to suppress noise and demodulate signals at 2.176 MHz. Switching transients from the digital I/O on the VL side can be coupled into the sensitive analog circuitry powered by VCC. These transients can cause ripple on the supply, which may affect the analog functions, such as the accuracy of the receiver's demodulation.

    Suggestion: Place a ferrite bead in series with the VCC rail, between the power source and the chip's decoupling capacitance. Ferrite beads are effective at filtering noise in the megahertz frequency range.

    Add multiple decoupling capacitors with different values in parallel, placed as close as possible to the VL and VCC pins. This lowers the power supply's impedance across a wider frequency range, which helps to smooth out high-frequency transient currents.

    Use a solid ground plane to minimize series resistance and inductance. Route the power nets as wide traces or planes to increase their mutual capacitance to the ground plane

  • +1
    TI__Guru* 79531 points

    Hi Matthew,

    Sunilbhai is correct. To also note, VL and Vcc need to be within the recommended operating conditions for them to be tied together. 

    VL is mainly used for the TTL logic levels and powering the VoH for those pins. Vcc is the more important of the two as it provides the reference voltages to the internal CMOS gates. I would still follow Sunilbhai's suggestions such as the parallel decoupling caps and trying to minimize any switching on the rails. 

    -Bobby