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Original question:

TMDS181: The schematic diagram review for TMDS181

TMDS181: Question about the TMDS181

Lumina Gui
Genius 3690 points
Part Number: TMDS181
Other Parts Discussed in Thread: SN65DP159, TXS0102

Tool/software:

Dear TI Engineer,

The main controller of our display product is FPGA, and the HDMI 2.0 signal input passes through TMDS181 to FPGA. Because it is a display equipment, so we need to match different signal sources. Now we are faced some quesion when we using the TMDS181, the details is as below:

1) When configuring the TMDS181, we sent the configuration for amplitude and EQ, as well as the effective bit for APPLY(bit [2] of 0Ah), but it didn't work and the image still flashed. We want to know what the configuration timing should be like, can you give us some suggestion for it?

2) For signals sent by some signal sources, a short HDMI cable can display normally (such as 1 meter, 1.5 meters), but replacing it with a long HDMI cable will display no signal (such as 3 meters, 5 meters). The FPGA will capture the printing information and prompt that the clock has been locked unstably.

Connect some signal sources, there is a picture, but there is obvious noise in the picture, or there is no display at all.

Our client has temporarily resolved the issue with the image by adjusting the SN65DP159 on the signal source end. They feedback is to first pull down one of the 5V interfaces of TMDS181, and then configure the value of the 0x0A address to 0x37. At this time, monitor the HPD signal transmitted from the display end, reset the amplitude and equalizer, and APPLY will work. We want to understand the principle of this, which 5V signal is pulled down, and what effect it has?

What we speculate is the OE port. Reset the chip and reconfigure the Retimer so that the video timing can be correctly recognized. Can you help confirm it?

3) If the TX end uses SN65DP159 to successfully configure the retimer, and the RX end uses TMDS181 to successfully configure the retimer, will the two retimers conflict, causing the FPGA end clock to fail to lock the signal?

4) The resolution recognized by my FPGA is 3840 * 62, and the clock recognized is 259M. The correct one should be 594M 4K60. The bandwidth used is the highest RGB 8-bit width. In this case, there is a problem with the configuration of TMDS181, can you give ys some suggestion for this issue?

The schematic of TMDS181 is as below:

TMDS181_SCH.pdf

Thanks,

Kind Regards

  • 0
    TI__Guru**** 177846 points

    Hi,

    In the schematic, the TMDS181 has its EQ pin pulled low. What happens if you leave the EQ pin floating so TMDS181 EQ automatically adapts? 

    Can you also pull the SIG_EN low to disable input signal detect? 

    The TXS0102 looks to be a level shifter only, but not a buffer and level shifter. You may have DDC I2C communication issue with long HDMI cable because the I2C setup and hold timing may get violated. You have multiple 4.7k pullup on HDMI_RX_SCL/SDA, but the spec requires the pullup resistor to be 47k.

    Thanks

    David