Other Parts Discussed in Thread: SN75176B
Tool/software:
Hello,
I am evaluating the SN75176B in a half-duplex RS-485 application and I have found a repeatable behavior on the RO (pin 1) output whenever toggling DE (pin 3) low and nRE (pin 2) low at the same time (to switch from transmit to receive).
Observed behavior
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At t=0, DE=1 / nRE=1 → driver enabled, receiver disabled. RO is high-Z (pulled externally to 3.3 V).
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When DE goes low and nRE goes low simultaneously:
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After ~15–40 ns, RO goes LOW.
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RO remains LOW for ~20 µs, even though the bus (A/B) is idle with bias resistors (4.7 kΩ pull-up on A, 4.7 kΩ pull-down on B).
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After ~20 µs, RO transitions HIGH as expected (A>B idle bias).
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When DE=1 / nRE=1 again, RO returns to high-Z (3.3 V pull-up).
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This behavior repeats consistently.
Measurements
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Scope captures attached show DE/nRE (yellow) and RO (green).
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At 9 600 baud (≈104 µs/bit), this is tolerable, but at 115 200 baud (8.7 µs/bit) the 20 µs LOW pulse is longer than a bit time and causes issues.
Schematics
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Attached simplified schematic:
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Bias resistors: A→+5 V (4.7 kΩ), B→GND (4.7 kΩ).
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RO pulled to 3.3 V via 10 kΩ and diode level-shift.
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Direction control: DE and nRE tied together via a BC817 transistor stage.
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Line protection: CMC + TVS.
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Questions
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Is this ~20 µs LOW at RO an expected behavior of the SN75176 family when toggling DE/nRE together?
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Is there an internal delay in the receiver comparator that explains why RO outputs LOW until the bus bias fully settles?
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What is TI’s recommended workaround?
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Add a delay between DE low and nRE low (so the receiver is enabled later).
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Use stronger bias resistors to speed up line settling.
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Or use a newer RS-485 transceiver with failsafe inputs that guarantees RO HIGH in idle?
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Any clarification or application notes would be very helpful.
Thanks in advance,
