SN65DSI84: SN65DSI84 : with Raspberry Pi CM4S + AUO P370IVN02.2 – Test pattern works, but no video output

Part Number: SN65DSI84

Tool/software:

Hello,

I’m working with the SN65DSI84 bridge chip to drive an AUO P370IVN02.2 panel using a Raspberry Pi Compute Module 4S.

The strange thing is:

In test pattern mode, everything looks fine. The LVDS clock and data lines are active, and the panel shows the internal pattern.

But with real video input (DSI), only the LVDS clock comes out. The data lines stay inactive, even though I can see that DSI clock and data are present on the input side.

PLL lock is OK. I’ll attach my i2cdump and DTS settings so you can see exactly what I’m using.

/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/bcm2835.h>

/ {
    compatible = "brcm,bcm2835";

    /* PWM0 function */
    fragment@0 {
        target = <&gpio>;
        __overlay__ {
            pwm_pins: pwm_pins {
                brcm,pins = <18>;
                brcm,function = <BCM2835_FSEL_ALT5>; // PWM1_0
                brcm,pull = <0>;
            };
        };
    };

    fragment@1 {
        target = <&pwm>;
        __overlay__ {
            pinctrl-names = "default";
            pinctrl-0 = <&pwm_pins>;
            assigned-clock-rates = <50000000>;
            status = "okay";
        };
    };

    fragment@2 {
        target-path = "/";
        __overlay__ {
            backlight_lvds: backlight {
                compatible = "pwm-backlight";
                pwms = <&pwm 0 1000000 0>; // 1KHz
                brightness-levels = <0 1000>;
                num-interpolated-steps = <1000>;
                default-brightness-level = <400>;
                enable-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>;
            };

            panel: panel {
                compatible = "panel-lvds";
                backlight = <&backlight_lvds>;
                label = "AUO:G156HAN";
                dual-link;
		
                width-mm = <904>;
                height-mm = <254>;
                data-mapping = "vesa-24";

                panel-timing {
                    clock-frequency = <45000000>;
                    hactive = <1920>;
                    hsync-len = <162>;
                    hfront-porch = <80>;
                    hback-porch = <80>;
                    vactive = <540>;
                    vsync-len = <15>;
                    vfront-porch = <15>;
                    vback-porch = <15>;
                };

                ports {
                    #address-cells = <1>;
                    #size-cells = <0>;

                    port@0 {
                        reg = <0>;
                        dual-lvds-odd-pixels;
                        panel_in_a: endpoint {
                            remote-endpoint = <&bridge_out_a>;
                        };
                    };

                    port@1 {
                        reg = <1>;
                        dual-lvds-even-pixels;
                        panel_in_b: endpoint {
                            remote-endpoint = <&bridge_out_b>;
                        };
                    };
                };
            };
        };
    };

    fragment@3 {
        target = <&i2c0if>;
        __overlay__ {
            #address-cells = <1>;
            #size-cells = <0>;
            status = "okay";

            bridge@2c {
                compatible = "ti,sn65dsi84";
                reg = <0x2c>;
                vcc-supply = <&vcc_1v8>;
                enable-gpios = <&gpio 42 GPIO_ACTIVE_HIGH>;

                ports {
                    #address-cells = <1>;
                    #size-cells = <0>;

                    port@0 {
                        reg = <0>;
                        bridge_in: endpoint {
                            remote-endpoint = <&dsi_out>;
                            data-lanes = <1 2 3 4>;
                        };
                    };

                    port@2 {
                        reg = <2>;
                        bridge_out_a: endpoint {
                            remote-endpoint = <&panel_in_a>;
                        };
                    };

                    port@3 {
                        reg = <3>;
                        bridge_out_b: endpoint {
                            remote-endpoint = <&panel_in_b>;
                        };
                    };
                };
            };
        };
    };

    fragment@4 {
        target = <&dsi1>;
        __overlay__ {
            #address-cells = <1>;
            #size-cells = <0>;
            status = "okay";

            port {
                dsi_out: endpoint {
                    remote-endpoint = <&bridge_in>;
                };
            };
        };
    };

    fragment@5 {
        target = <&i2c0if>;
        __overlay__ {
            status = "okay";
        };
    };

    fragment@6 {
        target = <&i2c0mux>;
        __overlay__ {
            status = "disabled";
        };
    };

    fragment@7 {
        target-path = "/";
        __overlay__ {
            vcc_1v8: vcc_1v8 {
                compatible = "regulator-fixed";
                regulator-name = "vcc_1v8";
                regulator-min-microvolt = <1800000>;
                regulator-max-microvolt = <1800000>;
                regulator-always-on;
            };
        };
    };
};

 

No size specified (using byte-data access)
     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f    0123456789abcdef
00: 35 38 49 53 44 20 20 20 01 00 83 28 00 01 00 00    58ISD   ?.?(.?..
10: 26 00 32 00 00 00 00 00 4c 05 03 00 00 00 00 00    &.2.....L??.....
20: 80 07 00 00 1c 02 00 00 21 00 00 00 2c 00 00 00    ??..??..!...,...
30: 05 00 00 00 94 00 0f 00 50 00 02 00 00 00 00 00    ?...?.?.P.?.....
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
f0: 00 00 00 00 40 00 00 80 00 00 00 00 00 00 00 00    ....@..?........

 

Any advice would be really helpful. Thanks a lot!

  • Hello, 

    Due to US public holiday, support will resume on Tuesday, September 2nd. Thank you for your patience. 

    Regards, 

    Logan

  • Hi Ahn Jinsu,

    With the DSI input video, is the device programmed with the initialization register settings from the DSI tuner tool? 

    The datasheet "7.4.3 Initialization Sequence" has details about the start-up power up and programming sequence. Please check whether these steps are followed, including the steps for DSI CLK and data lane states:

    "After power is applied and stable, the DSI CLK lanes MUST be in HS state and the DSI data lanes MUST be driven to LP11 state"

    Is the LVDS clock output frequency the same frequency as expected and matching the frequency of the test pattern mode?

    Best regards,
    Ikram