DP83867IR: IBIS model verification

Part Number: DP83867IR
Other Parts Discussed in Thread: AM6442, DP83869, TMDS64EVM

Tool/software:

Hi,

In the IBIS model for DP83867IRRGZT, pin 15 (X_I) is marked as NC, but the simulation wizard shows Vih as 2 V and Vil as 800 mV, which doesn’t match the 1.8 V logic level I’m using. The same issue is seen in the AM6442 processor, where pin C21 is also marked NC in the IBIS model. I’ve used the latest IBIS models from your website, and changing Vih/Vil values seems to affect undershoot/overshoot in simulations. Could you please clarify this? I will provide the snapshot for your reference.

  • Hi, 

    For DP83867, please use DP83869 IBIS model for that pin specifically. DP83869 IBIS correlates with DP83867 IBIS on this pin. 
    I will defer the question on AM6442 to the Sitara team. 

    Best,
    J

  • Hello Fhthima,

    Can you confirm if you plan to use crystal + infernal oscillator .

    The the internal oscillator, the oscillator is internal and you need to select the crystal and passive as per the data sheet.

    I am not sure on the need for simulating the Xi.

    Can you please elaborate the use case.

    Regards,

    Sreenivasa

  • Hi J, 

    For DP83867, please use DP83869 IBIS model for that pin specifically. DP83869 IBIS correlates with DP83867 IBIS on this pin. 
    I will defer the question on AM6442 to the Sitara team. 

    For the DP83867 the clock input is a fixed 1.8V input and does not scale with IO.

    Would the Xi still be compatible with DP83869 ?

    Regards,

    Sreenivasa

  • Hello Fhthima,

    NC is the expected connection for the AM64x family of processors. This is the crystal or oscillator input. We do not provide any IBIS models for the clocking section IP of the processor.

    Regards,

    Sreenivasa 

  • Hi Sreenivasa, 

    XI pin in 869 scales with three input voltages: 1.8, 2.5, and 3.3V and is compatible with 867. 

    Best,
    J


  • Hello J,

    Thank you.

    Regards,

    Sreenivasa

  • Hi,

    We are designing a custom board with reference to the TMDS64EVM. In the EVM, the AM6442 processor receives the clock input at pin C21 from the clock buffer. I am performing post-SI analysis for the EVM, and while analyzing the clock pin, I noticed an issue. Could you please clarify why the XI pin, which is marked as NC in the IBIS model?

    Regards,

    Fhanitha M

  • Hello Fhthima,

    Could you please clarify why the XI pin, which is marked as NC in the IBIS model?

    NC is the expected connection for the AM64x family of processors. This is the crystal or oscillator input. We do not provide any IBIS models for the clocking section IP of the processor.

    I do not have additional inputs. In case you are aware of ant SOC that has an IBIS model for the Xi, please chare. This is the standard approach. 

    In the EVM, the AM6442 processor receives the clock input at pin C21 from the clock buffer. I am performing post-SI analysis for the EVM, and while analyzing the clock pin, I noticed an issue.

    Please add details on the issue

    Regards,

    Sreenivasa