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TCAN4550: Rising time and Fall time requirements

Yishan Chen
Intellectual 1670 points
Part Number: TCAN4550

Tool/software:

Hi Team,

Customer is asking about the rising time and fall time requirements.

I have already checked this E2E link:

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1541640/tcan4550-clarification-on-rise-fall-time-vs-bit-width-requirements?tisearch=e2e-sitesearch&keymatch=TCAN4550%20fall%20time#

Could you please check if my understanding is right or not?

The rising time and fall time is more relative to TXD_INT/RXD_INT bit width time.

Basically, if we can keep the rising time/fall time within the bit width(Time) of TXD_INT/RXD_INT, then the fall time/rise time is acceptable.

For example, if the bode rate is 1Mbps, which means the bit width is 1uS of TXD/RXD, then once the rising time(from 0.5V to 0.9V) is <1uS, then the rise time is acceptable.(Maybe need some buffer, but overall is good)

Thank you,

Yishan Chen 

  • 0
    TI__Mastermind 33050 points

    Hi Yishan,

    I don't know if you are talking about the rise and fall times on the internal TXD and RXD signals, or about the CANH and CANL signals.  Either way, the rise/fall times need to be much faster than 1us if you want to achieve 1mpbs bit rate.

    The internal TXD and RXD bit times directly related to the CANH and CANL differential voltage level.  Therefore the CAN rise/fall times must be fast enough to cause the internal RXD signal to change states for a specific amount of time (Tbit) related to the bit rate.  If the CAN bus rise and fall times are to slow, then the internal RXD signal will not have a large enough Tbit period for the controller to properly sample the data without generating errors.

    The datasheet doesn't specify 1Mbps, but for 2Mbps, the Tbit period is a minimum of 400ns.  Since the 2Mbps has a nominal bit width of 500ns, this allows for a maximum total rise/fall time of approximately 100ns, or Trise = 50ns and Tfall = 50ns.

    Regards,

    Jonathan