DP83822H: DP83822HRHBR related issues

Part Number: DP83822H

Tool/software:

Hello,

Problem 1: The customer uses FGPA (ZYNQ) to test DP83822HRHBR. If the RGMII interface is not connected to the FPGA, the PHY can be linked to the upper computer. If the RGMII is connected to the ETH0 pin of the FPGA, regardless of whether there is a driver on the FPGA, the PHY cannot be linked to the upper computer.

Problem 2: The RXD pin is not configured with pull-up and pull-down resistors. If connected to an FPGA, the address is not the default 01, but 1f, which means that the addresses of the RXD pin should all be 1. The customer tried to configure a 4.7K pull-down resistor for the RXD pin, but the address became 01, which should also be incorrect.

Please help analyze the reason, thank you!

  • Hi,

    Can you please share the schematic for review?

    Thanks

    David

  • Hello,

    1. The schematic diagram is shown below.


    2. During customer debugging, it was found that the FPGA had an initial pull-up setting, which resulted in an incorrect initial state of the RX pin and address issues. The FPGA cancelled the pull-up setting and the problem was resolved.
    3. Now the RXC pin needs to be connected to a 10pf capacitor to GND, which can be linked up. The customer suspects an impedance issue, please help analyze it.

    Thanks!

  • Hi,

    Please use the attached spreadsheet to double check the DP83822 strap pins are being configured correctly. Please also dump out register 0x467 and 0x468 to check the strap setting. Please note 0x467 and 0x468 are extended registers and require the use of extended register access to read the value. 

    snlr053.zip

    Now the RXC pin needs to be connected to a 10pf capacitor to GND, which can be linked up. The customer suspects an impedance issue, please help analyze it.

    I assume this is the PHY link up to its Ethernet link partner? Can they measure the RXC with and without 10pF capacitor using a scope?

    Thanks

    David