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DS90UB948-Q1: The application issues of chips

Tonyx.wu
Genius 3965 points
Part Number: DS90UB948-Q1

Tool/software:

Please explain in detail how to configure this mode. Thank you!

  • 0
    TI__Mastermind 19215 points

    Hi Tony,

    This should be possible with OLDI Port 1 and Port 0 active to achieve the diagram you have shown where RIN0 > D4-D7.

    The replicate feature should be employed here, as the content coming into RIN0 will be replicated at both Port 0 (unused) and Port 1.

    Depending on the MAPSEL you will need for the timing configuration, this will either be No. 3 or No. 7.

    Reminder of MAP_SEL modes are shown below:

    Please let me know if you have any questions!

    Best,

    Miguel

  • 0 in reply to Miguel Bolante
    Prodigy 10 points

    hi Miguel Bolante

    There is no LVDS signal output now,Register configuration is 0x34=0x03,0x49=0xe3。

  • 0 in reply to liguo cui
    TI__Mastermind 19215 points

    Hi Liguo,

    Register 0x34 refers to the RX mode on the 948. Is there a serializer sending video through the FPD-Link at this time?

    • We can evaluate the status of lock from the original submission.

    Can you please provide a block diagram and a register dump of the system to confirm the settings? 

    For register 0x49:

    7 = MAPSEL = H

    6 = MAPSEL overwrite enabled

    5 = MAPSEL overwrite = H

    4-2 = Reserved

    1-0 = Replicate FPD-OLDI Output

    Best,

    Miguel