DP83822H: PHY is not transmitting out the ethernet frame in RMII mode.

Hi, 
Register 0x0001 shows that there is no link. If there is no link, the PHY will not be sending packets out. 

Have you tried plugging the FPGA to a link partner and ping the link partner?
What RMII mode is the PHY in? Is it RMII master or slave mode?

Could you share us your schematic so we can check if there's any connection error? Can you receive packets without any issues?
Please feel free to message me your schematic. I've sent you a friendship request. 

Best,
J

Hi J,

Thanks for the reply. Here is the schematic.

Hi J,

One more query. Is it required to provide soft reset after configuring the PHY? Which register should be used for reset, X00 or X1F? What should be the appropriate value to be write for reset?

Hi, 

Soft reset is recommended but is not necessary. Please use 0x1F = 0x4000 to soft reset the PHY. 

If you could answer the questions below, that would be very helpful understanding what your test setup is. 

J said:

Have you tried plugging the FPGA to a link partner and ping the link partner?

J said:

Can you receive packets without any issues?

In addition, are you not seeing any signals on the RMII TX lines also, or is it just on the MDI TX line?
Have you tried putting the PHY in MII loopback mode and verify if the MII side of the PHY is okay?


Below are the comments on the schematic:
1. It looks like signal connections were meant for MII, not RMII. Is pin 1 connected to the MAC's clock pin?
2. The PHY has internal termination so it does not need 33ohm resistors in the RX line. 

If pin 1 is not connected to the MAC's clock pin and the MAC is driving the 25MHz clock into the PHY, I will recommend to put the PHY in RMII follower mode and input 50MHz clock into the PHY to make RMII work. Otherwise, RMII will not work in the current design. 

Best,
J

Hi J,

Below are the answers to the questions you asked and some more details.

1. No, I have not tried link partner yet with FPGA.

2. Yes, I can receive packets.

3. I am receiving 50MHz clock form PHY on pin 1 (RX_D3). I am using this clock to generate ethernet frame and sending it to the TX [1:0] pins, with TX_EN. The transmit data is changing at the falling edge of this 50MHz clock.

I am attaching new values of PHY registers.6431.dp83822h_settings.xlsx

Our application requires RMII 100mbps full duplex mode. As per the schematic that I shared with you earlier, can you suggest us what should be our register settings.

-

Thank you,

Pulkit

Hi Pulkit, 

For RMII 100M full duplex, I suggest the following register setting:
0x0004 = 0000 0001 0000 0001

This will only advertise 100M full duplex link in auto-negotiation. Rather than forcing link, I suggest to advertise one speed in auto-negotiation since auto-negotiation is a very robust algorithm. 

Best,
J

Hi J,

I configure the device with the recommended settings. Here are the details:

BMCR (0X0000) = X3100

ANAR (0X0004) = X0101

I am sending a sample ethernet packet to the PHY from FPGA. The packet is:

frame (0 to 92) =

(x"AA", x"AA", x"AA", x"AA", x"AA", x"AA", x"AA", x"AB",
X"FF", X"FF", X"FF", X"FF", X"FF", X"FF",
X"DE", X"AB", X"22", X"33", X"44", X"55",
X"08", X"06",
X"45", X"00",
X"00", X"44",
X"12", X"34",
X"00", X"00",
X"40", X"11",
X"23", X"B4",
X"C0", X"A8", X"01", X"64",
X"C0", X"A8", X"01", X"0E",
X"C0", X"00",
X"C0", X"01",
X"00", X"30",
X"00", X"00",
X"01", X"02", X"03", X"04", X"05", X"06", X"07", X"08", X"09", X"0A", X"0B", X"0C", X"0D", X"0E", X"0F", X"10", X"11", X"12", X"13", X"14", X"15", X"16", X"17", X"18", X"19", X"1A", X"1B", X"1C",
X"1D", X"1E", X"1F", X"20", X"21", X"22", X"23", X"24", X"25", X"26", X"27",
X"9D", X"09", X"82", X"C5");

tx_byte = frame(byte_index)

I am sending transmit pairs as :

TXD(1) <= tx_byte(7);
TXD(0) <= tx_byte(6);

TXD(1) <= tx_byte(5);
TXD(0) <= tx_byte(4);

TXD(1) <= tx_byte(3);
TXD(0) <= tx_byte(2);

TXD(1) <= tx_byte(1);
TXD(0) <= tx_byte(0);

TXD[1:0] changes on falling edge of the 50MHz clock (provided by PHY on via pin-1)

Is there anything that you see is wrong? Please help.

-

Thanks,

Pulkit

Hi Pulkit, 

Is TX_EN going high when you send the data?
Can you verify the timing below?



Best,
J

Hi J,

Yes TX_EN is going HIGH and this timing is satisfied. The data and enable changes on falling edge on the XI clock.

Despite of configuring for 100 mbps, the PHYSTS values is X0002, that shows it is in 10mbps mode and link is not established.

I am clueless on this. My assumption is that even the frame does not have any meaning full data, but proper preamble and SFD, the Wireshark at the other end must show some values receiving.

-

Thanks,

Pulkit

Hi Pulkit, 

That is weird. 
I would not trust the speed/duplex status when the link is not established. 
After writing the register, have you restarted the autonegotiation? (bit 12 of 0x0000 goes high).

The link should be established without the FPGA support. The PHY itself will establish the link with the link partner. Can you verify that the link partner advertises 100M full duplex? 

Best,
J

Hi J,

After writing, I am reading back the BMCR and it is showing X3100, that indicates auto negotiation is enabled.

The connected PC on the other end of the board shows nothing on wireshark.

How do i verify that the link partner advertises 100M full duplex?

-

Thanks,

Pulkit

Hi Pulkit, 

If this is linux PC, you can use ethtool <interface name> to show overall status of the ethernet port. 
It should say something in the line of "advertised speed"

Best,
J

Hi J,

I will check and update you. It is a windows PC.

-

Thanks,

Pulkit

Hi Pulkit,

If this is the case, I assume it should have default autonegotiation for all speeds, but please do check. 
Did it link up in 100M when all speeds were previously advertised on DP83822?

Best,
J