DP83825I: DP83825I Timing and Reset Questions

Tool/software:

DP83825I Timing and Reset Questions

Hello,

I am working with the DP83825I Ethernet PHY and have a couple of questions regarding its timing and reset sequence. I've reviewed the datasheet, but I'm looking for clarification on a few specific points to ensure a robust design.

Q1: MDC/MDIO Timing and Reset Requirements

The datasheet specifies a maximum power-up time (T4​) of 50 ms and a maximum hardware reset time (T2​) of 2 ms. I need to understand the precise timing relationship between the management data input (MDC) and these events.

• Does the MDC signal need to be stable and ready after the maximum power-up/reset time, or can it be active before this timing is complete?

• Is it acceptable to have the MDC signal active even before the VAVDD​ power supply is stable or before the RESET_N pin is asserted?

Q2: Reset and MDIO Kernel Module Sequence

I'm implementing a hardware reset sequence and need to clarify the correct order of operations with the software. The reset procedure involves a RESET_N toggle from HIGH to LOW for 25 µs.

• What is the recommended sequence: Should I load the MDIO kernel module and its associated drivers before performing the hardware reset, or should I perform the hardware reset and then load the module?

• Please clarify the correct sequence to ensure the kernel driver can reliably communicate with the PHY after a hardware reset.

Thanks