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DP83848I: CPU and PHY are released simultaneously

Okutsu
Intellectual 260 points
Part Number: DP83848I

Tool/software:

Hi, Team.

We have received an inquiry from one of our customers regarding the Ethernet PHY device DP83848IVV.

Operating Environment:

  • Connected CPU: Renesas R7S721001VCBG (RZ/A1H microcontroller)
  • Interface: MII
  • The CPU and PHY are released from reset simultaneously using the same reset signal.

Observed Behavior:

  • After the reset is released, reading the registers of the DP83848I consistently returns 0xFFFF.
  • The PHY appears to remain in a connected state, even though no Ethernet cable is physically connected.

Based on these symptoms, we suspect that the device may be operating in isolation mode.

We understand that it may be difficult to determine the root cause based solely on the information provided above. However, we would greatly appreciate your expert opinion on this matter, as well as any suggestions regarding additional information or diagnostics that may be helpful.

Furthermore, if the device is indeed in isolation mode, could you kindly advise whether there is a procedure to transition it back to normal operation?

Best regards,

  • 0
    TI__Genius 13026 points

    Hi,

    Because this part is rather old, we cannot provide support beyond information that is publicly available.

    If the device is in isolation mode, it most likely has its internal packet generation and loopback enabled. However, in this case, the PHY’s register should still be accessible.

    How many PHYs/boards are affected? Could you share us your schematic so we can better look at this problem? If this happens only on one PHY, have you tried resoldering the PHY? This could be a soldering issue if al hardware connections are correct.

    Best,

    J