Tool/software:
We are designing an Ethernet switch where the DP83826 is implemented as the Ethernet PHY for the upstream interface. During the circuit design, we have a couple of doubts that need clarification:
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Should the CEXT pin be connected to a 2 nF capacitor, as specified in the datasheet?
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Please review the attached schematics. Should we strictly follow the power-up sequencing as mentioned in the datasheet?
Your guidance on these points will help us proceed with the design confidently.