XIO2001: PRSTn resets for not apparent reason

Part Number: XIO2001

Tool/software:

I have a new design that I am getting intermittent results on enumeration of cards on the cPCI port.  When I look at the signals I see the (cPCI reset) PRSTn signal on the cPCI side is switching high and low over a few times over a few second period.  It does this anywhere from 2 or 3 to 10 times.  I verified the power up sequence meets the data sheet.  The datasheet does not specify when GRSTn should get released in relation to the power up sequence.  I have experimented with it before, after, and at the same time as (PCIe reset) PERSTn, but it does not make a difference.  The activating and de-activating of PRSTn does not seem to correlate to anything else in the system.  

When should GRSTn be released in relation to the rest of the power up diagram?

What other connections to the chip can I look at that would cause the PRSTn to toggle? The power rails, PERSTn, GRSTn, and the PCIe clock all look good.

Frank

  • Hi Frank:

        GRST is global reset for XIO2001, it reset all control registers, state machines, sticky register bits. GRST  should de-assert  after 33.v and 1.5v supply at stable.

         PERST  is to generate a PCI Express reset and to signal a system power good condition, it will not reset  sticky register bits.

              PERST cannot be deasserted until the following two delay requirements are satisfied:

    • Wait a minimum of 100 μs after applying a stable PCI Express reference clock. The 100-μs limit satisfies the requirement for stable device clocks by the deassertion of PERST.

    • Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for stable power by the deassertion of PERST.

        PRST is PCI reset for secondary PCI bus. after GRST complete, the bridge asserts PCI bus reset ( PRST).

       System software has the ability to assert and deassert the PRST terminal on the secondary PCI bus interface as well

    Best

    Brian