• State Resolved
  • Replies 3 replies
  • Subscribers 33 subscribers
  • Views 43 views
  • Users 0 members are here
Support feedback
Options
Options
Related

DS90C031QML-SP: Design considerations for DS90C031QML input stage

Pierre Robitaille
Prodigy 10 points
Part Number: DS90C031QML-SP
Other Parts Discussed in Thread: DS90C031QML

Tool/software:

Hi. 

We are using DS90C031QML in our design. The chipset is supplied by 5V. We are constrained to go with this chipset for Radiation capabilities and part availability reasons. 

The main problem is that our MCU is supplied by a 3.3V  power supply and its digital outputs are bounded to the 3.3V domain.

Looking at the DS90C031QML datasheet, one can see that the logic levels are 0.8 and 2V for VIL and VIH respectively. The CMOS capabilities of the MCU are ok for this. 

However, one can see that the DS90C031QML datasheet also specifies a fail safe circuitry at the inputs of the line driver. This creates a power feed risk between the MCU and the 5V power supply of the line driver. 

I was just wondering how could I model this input fail safe biasing circuit to design a level translator using discrete components. Can I model it using a 500 K pull up at the input ( dividing 5V by 10uA input current spec in the datasheet ) or is another model better ? 

Is it necessary at all to design a level translator in this case ? 

Thank you very much and have a great day.

Pierre

  • 0
    TI__Genius 9906 points

    Hi Pierre,

    Just to make sure I'm understanding your question properly, you are referring to the output tri-state mode where the DOUT differential pins go high-impedance when the outputs are disabled, or are you wanting to know about single-ended input pin impedance (DIN pins)? 

    Regards,

    Matt 

  • 0 in reply to Matt Smith
    Prodigy 10 points

    Hi Matt. Thank you very much for the quick reply. I'm referring to the single ended input pin impedance. Is the fail safe biasing circuitry located at the input pin level and if so , how does it affects the input pin impedance ? Could it create a power feed between our 3.3V ( the IO driving the driver input pin ) and the 5V ( the driver's supply ) ? 

  • +1 in reply to Pierre Robitaille
    TI__Genius 9906 points

    Hi Pierre,

    The fail safe circuitry only applies to the output pins of the device (DOUT). The input pins (DIN) which you are referring to will not be at risk for the scenario you described. Just make sure to not exceed the pin's abs max limits (-0.3V to Vcc+0.3V). If you want to model the input current consumption, you can just use a 500 kOhm pull down resistor on the pin.

    Regards,

    Matt