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DS90UB913A-Q1: Power-Up sequencing changed from Rev.F to Rev.G

Fethi Ben Salah
Prodigy 10 points

Part Number: DS90UB913A-Q1

Tool/software:

Hello,

Texas Instruments DS90UB913ATRTVTQ1 - DS90UB913ATRTVRQ1 - DS90UB913ATRTVJQ1

In 2020 something related to Power-Up sequencing changed from Rev.F to Rev.G (November 2020) and we need to provide more information about this to the customer.
Is this true?

Best Regards,
Fethi

  • 0
    TI__Mastermind 27915 points

    Hi Fethi, 

    The difference between the revisions is documented in the Revision History located in section 4 of the datasheet as pictured below: 

    The change clarifies the power sequencing diagram that the voltage level threshold is PDB VIH rather than 90% of VPDB. Secondly, the local I2C workaround was updated to include an NCLK reset as the first step to the workaround if the t3 timing constraint is not met. 

    Best,

    Zoe

  • 0 in reply to Zoe Bison
    TI__Prodigy 10 points

    Hi Zoe,

    there was an internal misunderstanding regarding the datasheet change revision, on the cusotmer's side.

    The specific revision change they are interested in, and for which we require a deeper understanding of the impact, is the shift from revision E(2018) to F(2020) within the 2020 revision, focusing specifically on the impact of adding the maximum power up timing constraint  between VDD_ n and PDB (page 38 of the data sheet).

    Best regards,


    Fethi

  • 0 in reply to Fethi Ben Salah
    TI__Mastermind 27915 points

    Hi Fethi, 

    The power-up sequencing diagram was updated with Vdd_n to PDB to ensure reliable operation and link between serializer and deserializer. If this timing is violated, the below work around is recommended to be applied. 

    Best,

    Zoe

  • 0 in reply to Zoe Bison
    TI__Prodigy 10 points

    Thanks Zoe for the reply, could you help with the following customer asks:

    • Do you have any data on the frequency or probability of synchronization issues between the deserializer and serializer when the power-up timing is not followed?
    • Are there any known long-term implications or risks (e.g., reliability, component degradation) if the recommended power-up sequence is not followed?
    • Has this issue always existed but was only documented in the subsequent revision of the datasheet, or did it arise as a result of changes in the manufacturing process?
    • For example, could it be related to a change in the manufacturing facility or assembly line?
    • Do you have any statistics or field data showing how many customers have encountered this synchronization issue?
  • 0 in reply to Fethi Ben Salah
    TI__Mastermind 27915 points

    Hi Fethi,

    If power-up sequencing is not followed per the datasheet guidelines, the device will be operating outside of the set operating conditions and can behave non-deterministically. The issue has been present on the UB913 and was documented in a later version of the datasheet, there is no silicon change or manufacturing change pertaining to the power up sequencing. Our recommendation to customers is to follow the power-up sequencing as provided in the latest version of the UB913 datasheet, and if not possible to apply the local SW workaround. 

    Best,

    Zoe

  • 0 in reply to Zoe Bison
    TI__Intellectual 850 points

    Hello Zoe,

    the customer performed a further assessment and came back with the following questions:

    • Is the power-up constraint primarily a minimum delay (PDB after rails) or also a maximum delay? Does a long delay (e.g., 100 ms) pose any risk? The datasheet emphasizes the risk when timing is violated but does not distinguish between early vs late PDB assertion. Can TI provide an official clarification?
    • Does the internal state machine reset cleanly if PDB is asserted long after all rails are stable?
    • When sequencing is violated, are the effects transient only (e.g., link not coming up, intermittent lock) or can they lead to permanent damage or accelerated aging?

    Thanks and BR,

    Davide

  • 0 in reply to DavidLP
    TI__Mastermind 27915 points

    Hi Davide, 

    DavidLP said:
    Is the power-up constraint primarily a minimum delay (PDB after rails) or also a maximum delay? Does a long delay (e.g., 100 ms) pose any risk? The datasheet emphasizes the risk when timing is violated but does not distinguish between early vs late PDB assertion. Can TI provide an official clarification?

    The power up sequencing timing diagram is shown in the below figure from the datasheet: 

    t3 is defined as a minimum of 0ms, meaning VDDIO and VDD_n must be brought up at or before the PDB signal goes high. The maximum duration of t3 is 16ms as described in the below table: 

    If violating these timings, the device will be operating outside of datasheet conditions. In the case that the duration of t3 is longer, the local I2C workaround has been provided. Operating the devices outside of the datasheet range may result in non-deterministic performance. 

    DavidLP said:
    Does the internal state machine reset cleanly if PDB is asserted long after all rails are stable?

    No, if t3 timing maximum is violated the internal state machine for the forward channel will be stuck at an idle state. The local I2C workaround is to restart the state machine. 

    DavidLP said:
    When sequencing is violated, are the effects transient only (e.g., link not coming up, intermittent lock) or can they lead to permanent damage or accelerated aging?

    If t3 is violated, effects will be transient only and may result in the forward channel output not starting from the serializer. 

    Best,

    Zoe