DS125DF1610: Technical Inquiry Regarding DS125DF1610 Application

Neil Hung

Part Number: DS125DF1610
Other Parts Discussed in Thread: DS250DF410

Tool/software:

Hi Team,

One of our customers is currently evaluating a circuit design that incorporates your product DS125DF1610 to generate PRBS signals.

To support this evaluation, we have purchased your EVM board and performed some initial validation using the GUI tool provided by your company. So far, the results have met our expectations.

However, both we and our customer have some specific application-related questions that we would like to clarify.

Thank you in advance for your assistance.

Our questions are as follows:

With an RX input of 550 MHz, is it possible for the TX output to reach 5.5 GHz (550 MHz × 10) or 11 GHz (550 MHz × 20)? Is there a limitation that the TX frequency must be within 8× of the RX frequency?
If we use the DS250DF410 (supports up to 25 Gbps with x2 and x4 sub-rate) to design an external 20 Gbps source, does the ATE need to provide at least a 5 Gbps signal (20/4) to the retimer RX?
If the retimer can invert PRBS data, is it possible to control PRBS inversion via register settings?

Ex.

Normal PRBS7: 1000000100000110000101000111100100010110011101010011111010000111000100100110110101101111011000110100101110111001100101010111111

Inverted PRBS7: 0111111011111001111010111000011011101001100010101100000101111000111011011001001010010000100111001011010001000110011010101000000

We noticed that this device supports JTAG Boundary Scan testing and that a BSDL (Boundary Scan Description Language) file is available in the DS125DF1610 programming guide.

Could you also provide a STIL (Standard Test Interface Language) file?

Currently, we are using the TI GUI tool to control the device. We would like to transition to controlling the DS125DF1610 directly via SMBus using ATE I/O channels.

Could you kindly provide guidance or direct us to the appropriate contact for this?

We appreciate your support and look forward to your response.

Regards,

Neil Hung

Regards,

Neil

10 days ago

0 Gregory Kobyakov 9 days ago

TI__Intellectual 2085 points

Hi Neil,

I will check with the team and get back to you as soon as possible regarding these questions.

Best regards,

Greg

0 Gregory Kobyakov 5 days ago

TI__Intellectual 2085 points

Hi Neil,

1. We recommend using only div- 2^N for subrates.

2. Please see the table below for the supported data rates of the DS250DF410.

3. Yes, it is possible to invert PRBS output via register settings. This can be done through the inverting of sign bits of the FIR taps, and is described in Section 7.3.8 of the device datasheet.

4. We do not have an STIL file available for the device.

5. The programming guide for the device details the steps in configuration and controlling of the device via SMBus. Please let us know if there are any specific parts of configuration that need clarification.

Best regards,

Greg

0 Che-Jung Shih 4 days ago in reply to Gregory Kobyakov

Prodigy 50 points

Hi Gregory,

Thank you for your reply.

As fellow participants in the same project; we have a few additional questions we'd like to confirm:

1. Our original RX setting is 550MHz, if we expect to reach 11GHz TX frequency with a max divider of 8. Does that mean that the RX signal needs a faster data rate?

2. We intend to use the I2C interface to communicate between our instrument and DS125DF1610, instead of the SigCon Architect GUI.

If we already setup the correct electrical characteristics and timing for SCL&SDA, is there a specific flow or sequency we should follow? such as which register address need to send first? or can we directly send the address setting to register like the config generated by GUI interface?

Our setup config came from below:

DS125DF1610EVM: No signal was detect and and CDR remained unlocked - Interface forum - Interface - TI E2E support forums

Please help review this config as attachment and let us know if any setup modifications are needed.

config_register_20250918_LockCDR_EYE_PRBS_Quad2_3GHz.cfg

Thanks!

0 Gregory Kobyakov 3 days ago in reply to Che-Jung Shih

TI__Intellectual 2085 points

Hi Che-Jung,

1. A Div-16 sub-rate should work. In your case, this would require an input of 11 GHz/16 = 687.5 MHz. Please see the FAQ below for an explanation about enabling the PRBS generator for the device.

DS125DF1610 PRBS Generation FAQ

2. Are you currently able to successfully write/read registers via I2C? The scripts in the Programming Guide provide the accurate sequences to follow for configuration. I can take a look at the register map and let you know of any comments. Are there any issues you currently see after using this register configuration?

Best regards,

Greg

0 Che-Jung Shih 3 days ago in reply to Gregory Kobyakov

Prodigy 50 points

Hi Gregory,

1. Got it, just to double check, based on the figure below, is the max divider for the DS125DF1610 set to 8?

2. We've suffered an issue, but it's not related to I2C communication. We need to do "Apply to all channels" and do the "PRBS generator" every time when we start to send the signal to RX port.

Will the device automatically generate an interrupt when the signal is no longer present?

Thanks.

0 Gregory Kobyakov 2 days ago in reply to Che-Jung Shih

TI__Intellectual 2085 points

Hi Che-Jung,

1. For the div-16 input clock, the divider is not configured this way and relies on the 0x2F preset. Therefore, the PDIQ_SEL_DIV bits of register 0x18 should not be set. This is demonstrated in the script in the linked FAQ.

2. Could you please elaborate on this issue? Are you referring to the "Apply to All Channels" and "PRBS Generator" options in SigCon Architect GUI?

By default, the available interrupts are disabled. You must activate the interrupts you intend to use . To enable the loss of signal interrupt, SIG_DET_LOSS_INT_EN should be set to1.

Best regards,

Greg