Tool/software:
If AM6442x interfaces directly to PHY Transceiver, TP83867IR over RGMII, is it required to generate an external 125MHz RGMII reference clock source to AM6442x ?
It seems that AM64x can take 25MHz system clock then multiply it to 125MHz to RGMII TX Clock ?
In addition, if AM64x interface to the PHY Transceiver over RGMII; however, if PHY link-up with 100M speed (because only 2-pairs of MDI signals are link-up with a link partner), would expect to measure both RGMII TX_CLK and RX_CLK to be 25MHz (not 125MHz because link-up with 100M speed) ? However, it is still consider RGMII interface between AM64x and PHY ?
Last question, can AM64x RGMII interface (there are two RGMII ports; RGMII1, RGMII2) can add TX/RX delay since RGMII specification requires max 2ns clock skew requirement.