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DS90UB947-Q1: ds90ub947 pattern using select external clock + internal timing can not work

jianwei lan
Prodigy 20 points
Other Parts Discussed in Thread: ALP

solved already

  • +1
    TI__Mastermind 19575 points

    Hi Jianwei,

    Thanks for sharing this configuration script, I am happy to help review and analyze it.

    Can you please provide the following information to help me understand the system better?

    • Block diagram of the 947-928 devices
    • Display timing specifications

    I will first try to determine if the timing on the display is too strict for the internal clock generation of the 947 PATGEN. I may also be able to provide an example PATGEN script generated from the ALP GUI for the device.

    Best,

    Miguel

  • 0 in reply to Miguel Bolante
    TI__Mastermind 19575 points

    Hi Jianwei,

    It seems E2E did not attach your latest reply, but I have received the message internally.

    Hi Miguel,
ok now. update the script
ub947addr=0x1a
write_patgen_reg()
{
local addr=$1
local data=$2
i2ctransfer -f -y 3 w2@${ub947addr} 0x66 $addr
i2ctransfer -f -y 3 w2@${ub947addr} 0x67 $data
}
# static const struct drm_display_mode boe_ae123z7b_l13_wdp2_mode = {
# .clock = 116985,
# .hdisplay = 1920, 0x780
# .hsync_start = 1920 + 70*2, 0x780 + 0x8C
# .hsync_end = 1920 + 70*2 + 12*2, 0x780 + 0x8C + 0x18
# .htotal = 1920 + 70*2 + 12*2 + 4*2, 0x780 + 0x8C + 0x18 + 0x08 = 0x82C
# .vdisplay = 720, 0x2d0
# .vsync_start = 720 + 207, 0x2d0 + 0xCF
# .vsync_end = 720 + 207 + 2, 0x2d0 + 0xCF + 0x02
# .vtotal = 720 + 207 + 2 + 3, 0x2d0 + 0xCF + 0x02 + 0x03 = 0x3A4
# .vrefresh = 60,
# };
#disable pattern
i2ctransfer -f -y 3 w2@${ub947addr} 0x64 0x10
# 200Mhz / 2
write_patgen_reg 0x03 0x03
#h total[7:0]
write_patgen_reg 0x04 0x2C
#v total[3:0]
#h total[11:8]
write_patgen_reg 0x05 0x48
#v total[11:4]
write_patgen_reg 0x06 0x3A
#h active width[7:0]
write_patgen_reg 0x07 0x80
#v active width[3:0]
#h active width[11:8]
write_patgen_reg 0x08 0x07
#v active width[11:4]
write_patgen_reg 0x09 0x2d
#hsw
write_patgen_reg 0x0a 0x18
#vsw
write_patgen_reg 0x0b 0x02
#hbp
write_patgen_reg 0x0c 0x08
#vbp
write_patgen_reg 0x0d 0x03
#fps
write_patgen_reg 0x0f 0x1E
#select external clock + internal timing
i2ctransfer -f -y 3 w2@${ub947addr} 0x65 0x0c
#enable pattern
i2ctransfer -f -y 3 w2@${ub947addr} 0x64 0x15

    Allow me until EOD / Tomorrow morning to generate a new PATGEN script for you,

    If you have the display timing specifications, would you be able to share them?

    Thanks for your patience

    Best,

    Miguel