Can you give me the hint when you design the depth of the FIFO
In a system bellow.
The system consist of two blocks. They are primal block and secondary block.
The primal block generates pixel clock, video data as well as FVH sync pulses in SD, HD and
3G formats.
The secondary block receives FVH pulse and generates pixel clock such as 27MHz, 74.25MHz
74.25/1.001 MHz, 148.5MHz or 148.5/1.001MHz using LMH1983.
The video data is transferred between them using a FIFO.
FIFO is initialize with NO_LOCK signal from LMH1983.
When NO_LOC=’1’, FIFO is reset and when NO_LOCK=’0’, FIFO is in operation mode.
The question is that, at least, how much depth of FIFO is necessary for robust operation.
I suspect that the amount to the peak jitter included in the H Sync generated in the primal block
is the dominant (or only) factor when you decide the depth of the FIFO required in this system.
Please advise me if it is correct?
Another concern is that when the NO_LOCK is changed from ‘1’ (NO_LOCK) to ‘0’ (LOCKED),
PLL1 may not be clocked completely. Because the NO_LOCK may not indicate the exact lock
conditions of the PLL.
In average PLL is assumed to be locked, however, in microscopic instance there may be significant
phase error.
Please let me confirm that once NO_LOCk is de-asserted, the phase error between HSIN and output
clock never exceed certain value at nay instance.
Another word, you have not worry about the depth of the FIFO other than jitter included in the HSIN.
PS Please also advice me on the PLL loop filter components values.
The: LMH1983 data sheet recommends CP≈CS/20. In contrast evaluation board uses Cp=Cs/47.
Please let me know why Cs/47 was used as Cp instead of Cs/20.
Please also le m know the recommended range of Cs/Cp ratio.
