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DS90UB953-Q1: CLK_OUT

d_zero
Genius 4975 points

Part Number: DS90UB953-Q1

Tool/software:

Dear Team,

if using CLK_OUT when in STP mode and I2C voltage level is 3.3V

IDX 4  -> Vidx target voltage 1.224V -> Rbot= 100k , Rtop = 47k -> I2C 7-bit address is 0x19 , I2C 8-bit address is 0x32

1) Is it ok to use 100k for bottom res and 47k for top res?

2) The top res should be pulled to VDD_1P8_D ( pin25) , 1.8V?

3) When using the CLK_OUT pin with the upper resistors , what is the Vos ( output common-mode voltage) ? is it 1.224V ?

4) When using the CLK_OUT pin with the upper resistors , what is the Vod ( output voltage swing) ? 

5) I have to feed this CLK_OUT to  a clock input that accepts LVCMOS 3.3V , i assume i will need to do AC coupling and after that bias the signal? What would you propose?

CLK_OUT ( from SER) -> IDX pull-up/down -> AC coupling cap -> resistor bias network with Rt and Rb where Rt pulled to 3.3V -> series resistor -> clk input to the IC

or

CLK_OUT ( from SER) -> IDX pull-up/down -> series resistor -> AC coupling cap -> resistor bias network with Rt and Rb where Rt pulled to 3.3V  -> clk input to the IC

Best Regards,

d.

  • 0
    TI__Mastermind 30920 points

    Hi,

    d_zero said:
    1) Is it ok to use 100k for bottom res and 47k for top res?

    A minimum load impedance at the CLK_OUT/IDX pin of 35kOhm is required when using the CLK_OUT function. If 47k pullup and 100k pulldown is used, then the load impedance will only be ~31.97kOhm. This is why we recommend using 68.1k pullup and 137k pulldown for a load impedance of ~45.49kOhm.

    d_zero said:
    2) The top res should be pulled to VDD_1P8_D ( pin25) , 1.8V?

    IDX pullup resistor should be connected to VDD 1.8V supply.

    d_zero said:
    3) When using the CLK_OUT pin with the upper resistors , what is the Vos ( output common-mode voltage) ? is it 1.224V ?

    CLK_OUT is a 1.8V LVCMOS signal, so common-mode voltage is ~0.9V. If the load impedance is greater than 35kOhm, then the pullup and pulldown resistors will have minimal impact on logic high and low levels.

    d_zero said:
    4) When using the CLK_OUT pin with the upper resistors , what is the Vod ( output voltage swing) ? 

    See CLK_OUT specs from the datasheet.

    d_zero said:
    5) I have to feed this CLK_OUT to  a clock input that accepts LVCMOS 3.3V , i assume i will need to do AC coupling and after that bias the signal? What would you propose?

    Since CLK_OUT signal is already LVCMOS, I don't recommend AC coupling. A resistor bias network also cannot be used to effectively convert the clock signal to 3.3V LVCMOS. I recommend considering a level shifter or clock buffer IC to convert from 1.8V to 3.3V LVCMOS.

    Best,

    Lucas

  • 0 in reply to Lucas Wolter
    Genius 4975 points

    Dear Lucas,

    thank you for the answers.

    So if CLK_OUT is not used then i can use 100k pulldown and 47k pull up , and if it is used then i should use the suggested values from DS or calculate so that the impedance is greater then 35k ? If the CLK_OUT is not used is there a register that we can turn off the CLK_OUT?

    Do you have a recommended level translator or clock buffer for the LVCMOS 1.8V to LVCMOS 3.3V?

    Best Regards,

    d.

  • 0 in reply to d_zero
    TI__Mastermind 30920 points

    Hi D,

    Your understanding is correct. If CLK_OUT is unused, you can use any value pullup/pulldown resistors as long as the voltage level at the pin is within the range specified in the datasheet. If CLK_OUT is used, you can select any pullup/pulldown resistors as long as load impedance is greater than 35kOhm. The suggested resistor values in the datasheet satisfy the 35kOhm load impedance requirement and many customers stick to these values.

    If CLK_OUT is unused, it can be disabled by writing register 0x06=0x20. In this condition the output will remain static high or low.

    Regarding device recommendations, I suggest opening a new thread on the clocks and timing forum. I specialize in FPD-Link products.

    Best,

    Lucas