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Original question:

TIC10024-Q1: the meaning of Comparator detection time

TIC10024-Q1: Timing of /INT signal

Andreas Brugger
Prodigy 60 points
Part Number: TIC10024-Q1

Tool/software:

Dear Support Team,

can you please detail when the /INT-pin is raised in polling mode after confirmed SSC:

* immediately when the SSC is detected?

* when all enabled input channels are "scanned" (at the end of the application of the wetting current of e.g. IN23)?

* at the end of the polling cycle?

Please identify in the attached diagram, when the signal at the /INT-pin is raised.

What is the delay from SSC detection to /INT raised?

Best regards,

Andreas

  • 0
    TI__Mastermind 23600 points

    Hello Andreas,

    Please read Section 8.3.9.1 in the datasheet since /INT-pin pulled high will be different if you choose Static /INT or Dynamic /INT.

    Regards,

    Josh

  • 0 in reply to Joshua Salinas
    Prodigy 60 points

    Hello Josh,

    thanks a lot for your prompt answer.

    Please confirm for Static /INT Assertion Scheme:

    * /INT-pin is asserted in polling mode immediately after confirmed SSC                                                                                                                                   

    * the SSC detection to /INT-pin asserted is without delay after t_COMP

    * independent of the channel number

    * independent of the global timing (t_POLL_ACT_TIME. t_POLL_TIME)

    Thanks in advance.

    Best regards,

    Andreas

  • 0 in reply to Andreas Brugger
    TI__Mastermind 41166 points

    Hi Andreas,

    We are still looking into this question and will provide a response soon.

    Regards,

    Jack

  • 0 in reply to Andreas Brugger
    TI__Mastermind 23600 points

    Hello Andreas,

    The /INT pin is released on the rising edge of CS only if a READ command has been issued to read the INT_STAT register while CS is low, otherwise the INT will be kept low indefinitely

    Regards,

    Josh