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TCAN4550-Q1: TCAN4550-Q1 cannot get RF0N: Rx FIFO 0 new message technical support

Roy Chan
Expert 4130 points
Part Number: TCAN4550-Q1
Other Parts Discussed in Thread: TCAN4550

Tool/software:

Hello Application Team:

   we have design TCAN4550-Q1 , in the first time, we are trying to adding enable TX buffer interrupt after Tx send message complete. 

But we found RF0N: Rx FIFO 0 new message -> host cannot get any interrupt from TCAN4550-Q1 when Host send continuously CAN message after we adding  enable TX buffer interrupt code.  

The following coding is we are adding to enable the TX buffer interrupt get TC interrupt when CAN message is compete. could you please help give suggestion of register set flow of TCAN4550 ?

Our Requirement:

(1)Need to get  TCAN4550 TC interrupt to Host when Tx buffer complete:

(2)still need get  RF0N: Rx FIFO 0 new message interrupt while CAN message is keep to working after implement Item 1 requirement. 

Add TX buffer interrupt code get TC interrupt status when CAN message is compete as below 

  • 0
    TI__Mastermind 33410 points

    Hi Roy,

    Roy Chan said:
    But we found RF0N: Rx FIFO 0 new message -> host cannot get any interrupt from TCAN4550-Q1 when Host send continuously CAN message after we adding  enable TX buffer interrupt code.  

    I'm not sure what it means "to not get any interrupt."  What is the status of the nINT pin?  I assume this means it is not changing states causing the MCU to not recognize an interrupt event has occurred but does that mean it Is stuck High or stuck Low?  

    Is my understanding correct that you received the RF0N interrupt on the nINT pin Before you added the code to enable the TC interrupt bit as well?  Or did you always have trouble with receiving the RF0N interrupt as well?

    Can you please provide a list of the final register values so that I can review the final overall device configuration for errors?  This would be much easier to spot configuration issues than screenshots of code.

    One observation I have from the screenshot of your interrupt handler is that you appear to be using the TCAN4x5x_MCAN_ClearInterrupts(&mcan_ir) function for every interrupt bit that is getting handled.  Unless you have modified the code, I believe that the demo code uses this function to clear ALL set interrupt bits in the register.  If multiple bits are set in the register such as both the TC and RF0N bits, the code may be clearing the RF0N bit as part of the TC handler and prevent you from seeing the RF0N interrupt bit.

    I would suggest for debug to try to read the RX FIFO 0 Status Register 0x10A4 to verify the device is actually receiving messages into the RX FIFO 0 to make sure there isn't really an issue with receiving messages which would not cause the RF0N bit to be set.

    Regards,

    Jonathan

  • 0 in reply to Jonathan Nerger
    TI__Expert 4130 points

    Hello Jonathan:

       Thank you very much your explanation, we will double check after China National holiday, BTW.  I just saw the existing Linux driver as below of TCAN4x5x 

    on website, can we use this for coding review ? 

    https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/can/m_can

    thank you 

    Roy

  • 0 in reply to Roy Chan
    TI__Mastermind 33410 points

    Hi Roy,

    Yes I think you should be able to use those files for review.

    Regards,

    Jonathan