DP83867IS: DP83867ISRGZ to EG25G communication not working ( through SGMII interface )

Hi, 

NANDHA KUMAR said:

Specifically, Do we need to maintain any particular state on LED_0 ( pin# 47 ) & LED_1 ( pin# 46 ) pins on DP83867ISRGZ IC? to successfully enable SGMII interface? 

LED_0 has to be strapped to mode 2 for SGMII mode to be enabled (and mirror mode disabled) by default. However, I do not see that on the schematic. 

You can also check bit 11 of register 0x0010 to see if SGMII is enabled on the PHY.

If so, could you send us a register information of below registers:


We are looking into any FAE support available in the region. I will update you once I get any information. 

Best,
J

Hello J,

Thanks for your prompt response. 

Our current understanding is that, we need to strap the LED_0 pin to mode 2 to make the SGMII interface work. 

Also we hope LED_1 pin also needs to be strapped for Auto-Negotiation / Speed Select. is that correct? 

What should be the default hardware state that we need to maintain on these ( LED_0 & LED_1 ) pins? Can we follow the below strap values which refered from DP83867E SGMII EVM? Please suggest. 

J said:

You can also check bit 11 of register 0x0010 to see if SGMII is enabled on the PHY.

We hope register values can be read through the SGMII interface only. Currently the SGMII interface from ETH PHY is directly connected to the EG25G GSM modem so we don't have direct access to read the register values. We have requested the modem vendor to add this PHY IC on their library and test the same. So kindly allow us some time to reply on these register values. 

Is there any FAE available on our surrounding? Hope you are checking on this. Please do support. 

Hi,

If a given strap input is resistively pulled low then the corresponding output is configured as an active high driver. In the context of the 4-level straps, this occurs for modes 1, 2, and 3. Conversely, if a given strap input is resistively pulled high, then the corresponding output is configured as an active low driver. In the context of the 4-level straps, this occurs only for mode 4 as shown below.

The PHY registers have be accessed by the Serial Management Interface, not the SGMII interface.

Thanks

David

Hi David

Thanks for the suggession. Now we understood the HW state which we need to maintain for SGMII selection ( on LED_0 pin ).

On our application we are going to provide only 4 Wire output to the external device. ( Highlighted in below image ). 

So What should be the default HW state that we need to maintain on LED_1 ( Speed slection strap ). Also is there any guidelines for resitsor values we need to use on this starp? 

Can we use the same resistor values given in the above image reference? Kindly advice. 

Hello,

For 10/100M communication (only possible with 4-wire communication on MDI), it would be best to keep ANEG_SEL set to '0'. This would involve LED_1 in mode 1 or 2. 

Please refer to 4-level strap table resistance values for appropriate resistance selection. The series resistor (470) is a current limiting resistor and is subjective based upon LED circuit fundamentals.

Sincerely,

Gerome

Hello Gerome,

Thanks for the guidance, We will dick into this further and let you know the observation after experiment. 

Hello Gerome,

Thanks for the guidance, We will dick into this further and let you know the observation after experiment. 

Hi, 

Please let us know of any updates. 

Best,
J