DS90UA101-Q1: Could we support SPI, I2C, I2S, TDM, S/PDIF protocols?

Hi Leo,

I2C, I2S, and TDM are supported through this device.

What is the specific application use-case for the system needs? Maybe a block diagram might help visualize this.

I can base the recommendations off of this visualization.

Best,

Miguel

Hi Miguel,

Thanks for your reply.
Here is our system block diagram for your reference.
Could you please help to check if DS90UA101-Q1 is suitable for this architecture and share any circuit design suggestions for this application?

Thanks,
JH

Hi JH,

If the architecture requires all of the protocols defined in "Interface", we may need to further evaluate suggestions for accommodating S/PDIF and SPI communication.

Thank you for sharing your block diagram, please give me 1 business day to evaluate the options and suggestions.

Best,

Miguel

Hi JH,

Are all interfaces required simultaneously, or only some are needed at one time?

For example, will you need I²S and TDM and S/PDIF, or can I²S take the place of TDM and so on?

Same for I2C and SPI, are both functionalities needed or can you choose one or another?

Either way - the DS90UA101-Q1 and DS90UA102-Q1 are able to transmit the following signal protocols over the SER-DES Link:

• I²C
• I²S / TDM
• GPIO

If other functions are needed, additional FPD-Link III devices are able to pass through SPI through GPIO. Please let me know if the current solution may be sufficient, or if you have additional questions.

Best,

Miguel

Hi Miguel,

Following up on our integration plan: our antenna module will include a broadcast tuner (NXP-based, I²C + I²S/TDM) and a SDARS tuner (UART control + I²S audio). Only one audio source is active at a time on the IVI side.

We aim to keep a single FPD-Link III (DS90UA101-Q1 / DS90UA102-Q1) link over one cable carrying:

-I²S / TDM (main digital audio)

-I²C (control)

-GPIOs (reset/interrupt/source-select)

For SDARS UART control, we plan to place a small I²CUART bridge IC on the module side (no MCU), controlled through the UA101/UA102 I²C pass-through.

Could you please advise on the following?

Reference design / app note / pin mapping for combining I²C + I²S/TDM + GPIO on UA101/UA102 (single coax/STP).

Audio clock guidance: recommended register settings (polarity/phase, master/slave for BCLK/LRCLK/MCLK, TDM slot mapping), and any constraints we should be aware of.

I²C pass-through performance considerations when it’s also used to drive an I²CUART bridge (typical UART up to 115200 bps). Any notes on latency/throughput or reliability on the back channel.

If there’s a UA101/UA102 family device that supports native UART tunneling or an approved method using the back-channel/GPIOs for UART, please recommend it so we could avoid the bridge IC.

Layout/EMC tips for audio clocks and data (e.g., BCLK/LRCLK/MCLK routing, impedance targets, isolation from RF input), and any power/reset sequencing practices you recommend for the link.

Our intent is to keep one SERDES pair only while maintaining flexibility for customer IVI interfaces (I²S/TDM as main path, optional S/PDIF reserved).

Many thanks for your support and guidance,
JH SU

Hello JH SU,

Please allow me one business day to collect all the relevant feedback for this request, I can provide you a summarization of the current configuration and any additional details / guidance I find for these protocols with the FPD-Link III family.

Appreciate your patience!

Best,

Miguel