Part Number: DP83826I
Tool/software:
Hello
The Beckhoff "PHY selection guide" PDF describes following for the DP83826:
https://download.beckhoff.com/download/Document/io/ethercat-development-products/an_phy_selection_guidev3.1.pdf
Recommended configuration for Fast Link Down mode in CR3:
enable Bit 10 (Descrambler), Bit 3 (RX Error count) and Bit 2 (MLT3
error), and FLD_CFG2: Bit [5:0] = 0x08
Do I see it right that this couldn´t be realized with both PHYs only by strapping?
Each of the PHYs had to reconfigured by MDIO access for optimal setup of the PHY?
Kind regards
Thomas D.

