DP83867CR: DP83867 25MHz clock input circuit design

Hi Shane:

Thanks for the prompt answer.   You are reporting that no problems have come up.  But, that mean that there is a resistive bias circuit on the die to keep the mid point of the divided swing from floating around and going out of spec, or does it mean that the part does pretty good at continuing to operate even when the divider output drifts out of spec?

Best,

Farron

Hi Shane:

Thanks for the prompt answer.   You are reporting that no problems have come up.  But, that mean that there is a resistive bias circuit on the die to keep the mid point of the divided swing from floating around and going out of spec, or does it mean that the part does pretty good at continuing to operate even when the divider output drifts out of spec?

Best,

Farron

Hi Farron,

Device internals are not a typical customer ask, and are likely confidential to TI. We have characterized DP83867 with the datasheet recommended capacitive divider circuit, so I recommend proceeding with this as a reference. Please note the oscillator needs to meet the datasheet specs as well:

The capacitive divider isolates the XI pin from external DC bias, so the XI pin should not be seeing a significant DC average drift. This pin is designed to work with oscillators that meet the datasheet specs (table above) and I have not heard of this being a problem in the past. Are you seeing an issue with the XI pin on your board?

Best,

Shane

Hi Shane: 

We're not experiencing known problems with this, but after 40 years as a design engineer I've learned that operating out of spec and leaving the door open for problems means that occasionally they will occur.  I tried to show a couple of SPICE sims here to illustrate this possible problem.  But, using the Insert=>Image/Video/File tool just results in the message "File uploading not allowed". Whatever the technique is to paste images or post files is here, I cannot figure it out.  Another user interface issue here on E2E is that this window does not have a "Post" button.  It has a "Suggest as answer" check box and a Login button.  I have already logged in, but apparently that fact is lost in entering the E2E page.  That's how a reply can get posted twice, which then results in the system flagging it as spam.  

So, I'm reduced to explaining the possible problem verbally.  I set up the SPICE sim with a 3.3V 25MHz clock driving the capacitive divider.  A 10uA current source from the chip input to ground is placed (10uA being the spec'ed amount of leakage).  This current leak would cause continual downward drift on the clock input pin, except the voltage runs into the chip input protection diodes.  The result is a swing of 1.5Vpp, but with the low side at -0.4V and the high side at +1.1V.  The +1.1V is 300mV below the specified minimum high side peak of +1.4V.  

Fundamentally the problem is that a DC mid-point for the swing has not been established in this strictly AC coupling circuit where the output is between two capacitors.  If that is just a CMOS input gate on the die, then what establishes a DC operating point is the input protection that turns on when the swing drifts low or high and bumps into the protection diodes.  The low side protection kicks in if the 10uA is coming out of the pin, and the high side protection kicks in if the 10uA leakage is going into the pin.  

The potential problem is solved if a resistive divider is present on the input pin to establish a DC condition.  If there is not one on the die, then the customer should place one on the PCB. Either way, that centers the swing and allows meeting the specs in the data sheet for low and high swing voltages. 

Best, 

Farron

Hi Farron,

I do not believe that a 10uA current source from the pin to GND is accurate. If we go by the DC characteristics in the datasheet, the input current can go from a minimum of -10uA to a maximum of 10uA depending on external circuitry. If there are DC blocking capacitors on the input, as is the case with this capacitive divider, I would expect a negligible DC current flow into the pin:

To post images on E2E, click the grey 'upload button' in the Insert => Image/Video/File menu and select the file from your PC. Is this not working on your side?

Best,

Shane

Hi Shane:

The E2E system won't let me copy and paste into this text window (the image is grayed out), and when I try to upload a file it just gives me the error message "File uploading not allowed".  I asked ChatGPT to help me figure it out, and its final conclusion was just that it is an out of date system.  

As a former analog IC designer, I don't actually believe the 10uA leakage spec myself.  The leakage comes from the combination of gate leakage and reverse diode leakage from the protection circuits, which are nothing to do with external circuitry other than needing a leakage path to absorb the leakage.  10uA is probably just a convenient safe figure, but even if it is just 1uA, the same problem exists. If no DC potential is established on the input, the voltage on the mid point of the capacitive divider will drift high or low until the diode protection turns on and stops the drift.  The diode protection is then consuming some of the applied signal and reducing the peak to peak swing, which with the offset center point then fails the swing spec by about 300mV in the case of 3.3Vpp input to the divider.  With 2.5Vpp input the failure mode would be worse.  

Since your management apparently does not want you to confirm or deny a DC bias on the die, we'll assume there is not any and place an external divider.  

Thanks, 

Farron

Hi Farron,

I took our DP83867ERGZ-R-EVM into the lab today to test the XI pin and to see if I got the behavior you mentioned. I powered up the board and fed an external clock signal (Blue) into a capacitive divider to measure the signal near the PHY (yellow):

My capacitive divider isn't perfect, but the signal amplitude is reduced from around 3.16V to 1.24V. I can see there is about a 0.9V DC bias on the clock signal near the PHY. When I power off the PHY, that DC bias goes away, and I get the following waveform:

From these tests I can confirm the PHY does establish its own DC bias on the XI input, but I'm afraid I cannot share what internal circuitry in the PHY sets this bias. Hopefully this helps to answer your question.

Best,

Shane