Part Number: DS250DF230
Other Parts Discussed in Thread: DS280DF810
Hi,
I have few questions and uncertainties about the DS250DF230 with regards to PRBS generation with differing clock inputs.
I would like to generate a PRBS-31 signal at a data rate of 20Gbps as shown in the image below. I would like to do this with a 625MHz clock emulating an input NRZ data stream of 1.25Gbps. 20 / 1.25 is a 16x division.
Some forum posts suggest that this can be done. Evidence is found in posts 5, 6, and 7 (links and summaries below).
Other forum posts suggest that this cannot be done. Evidence is found in post 4 (link and summary below).
Page 28 of the DS250DF230 datasheet itself shows that data rates of less than 4.9Gbps by-passes the CDR, and so this suggests that a minimum clock speed of 2.5GHz (to emulate a 5Gbps data stream) is needed for accurate PRBS generation.
Will a 625MHz input clock be able to generate a 20Gbps PRBS signal?
Will this clock be treated as NRZ data with a data rate of 5Gbps so that one clock cycle looks like 00001111… repeating data?
Will jitter be much less if an input clock of 2.5GHz is used to generate a 20Gbps signal so that the data looks like 01… repeating data?
Forum post 1
e2e.ti.com/.../faq-ds280df810-why-is-25g-28g-retimer-prbs-generator-not-working
The DS280DF810 is very similar to the DS250DF230 and this FAQ states that a recovered clock from the CDR re-timer is needed for PRBS generation.
Forum post 2
e2e.ti.com/.../ds250df230-the-divider-setting
For the divider setting, does the divide by 8 and 16 setting bypasses the CDR? If this is done and the PRBS generator uses a recovered clock from the CDR, does that mean it will not be able to generate a PRBS signal if the divider is set to 8 or 16?
Forum post 3
e2e.ti.com/.../ds250df230-how-to-generate-a-prbs-signal
It is mentioned that to generate a 10.3125Gbps PRBS signal, a 10.3125Gbps / 8 = 1.2890625GHz clock is needed at the input. Does this mean that the clock must be fast enough to look like a div by 4 data stream of 2.578125Gbps?
Forum post 4
e2e.ti.com/.../ds250df230-ds250df230
On this post, it looks like a 322.265625MHz clock input cannot produce a PRBS signal output at 10.3125Gbps. /8 and /16 both bypass the CDR due to high sub-divisions and so no PRBS can be generated?
Forum post 5
e2e.ti.com/.../ds250df230-use-retimer-to-generate-and-check-prbs-signals
A TI engineer on this post states that a 25.78125Gbps PRBS signal can be generated if the input has an 805.66402MHz clock signal (equivalent to a 1.611328Gbps data stream). This is divided down by 16x.
Forum post 6
e2e.ti.com/.../ds250df230evm-prbs-configuration-at-6-375gbps
This post shows that a 6.375Gbps PRBS signal can be generated from a 398.4375MHz clock input. This is equivalent to a 796.875Mbps data stream. This is a division of 8.
Forum post 7
e2e.ti.com/.../ds250df230evm-a-problem-of-prbs-testing-with-ds250df230evm
This post answered by a TI engineer states that a PRBS signal can be generated down to a clock of 25.78125GHz / 64. Does this mean the minimum input data rate is 805.664Mbps (corresponding to a clock speed of 402.832MHz)? If so, this is a 32x division.
Regards,
Liang
