Part Number: DS92LV16
Hello,
Our system has an FPGA connected to a DS92LV16 SERDES IC. The FPGA drives the TCLK pin of the SERDES with a clock signal of 43.75 MHz.
The DIN[15:0] pins are driven by the FPGA with a pattern of an incrementing counter every cycle: 16x0000 , 16x0001, 16x0002, ... , 16xFFFF , 16x0000 , etc. The REFCLK pin of the SERDES is also driven with a 43.75 MHz clock signal. The SYNC pin is tied to GND, while RPWDN and TPWDN are tied to VCC. The voltage to the device seems clean.
I'm monitoring the LOCK signal from the SERDES and see that it's unstable (sometimes 3.3V, sometimes 0V).
Given my description, what might cause the SERDES IC to loose lock ?
