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SN75DP159: Pin 21 (EQ_SEL/A0) behavior when I²C Enable is High

ArTzy
Mastermind 19690 points

Part Number: SN75DP159

Hi Experts,

We are currently integrating your device and have a question regarding pin 21 (EQ_SEL/A0). According to the datasheet, this pin is used for equalization selection when I²C_EN/PIN = Low, and also serves as address bit 1 when I²C Enable = High.

Our concern is the following:

What happens if pin 21 (EQ_SEL/A0) remains unconnected when I²C Enable is High?
We need a reliable solution to avoid undefined states. Our plan is to tie the pin to GND, but in the meantime, we would like to confirm whether there is any internal weak pull-up or pull-down resistor connected to pin 21.

Follow-up Questions

  1. If pin 21 is left floating when I²C_EN = High, what default logic level does the device detect?
  2. Is there an internal weak pull-up or pull-down on this pin? If yes, what is its typical resistance?
  3. Could leaving this pin unconnected cause unpredictable behavior or affect the I²C address selection?
  4. Are there any recommended practices in the datasheet for handling unused EQ_SEL/A0 pins when I²C mode is enabled?
  5. Is there any risk of noise coupling into the pin if it remains floating?

Thank you.

Regards,
Luca

  • 0
    TI__Guru**** 183591 points

    Luca

    When I2C_EN/PIN = High, pin 21 is a 2 level pin to set the I2C address. In this case, you have to set it externally to (H) Logic high (pin strapped to VCC through 65-kΩ resistor) or (L) logic low (pin strapped to GND through 65-kΩ resistor).

    Thanks

    David