SN65DSI86: The DP display can't output normally

Hi Ikram

Thank you for your help, I have already reset the SN65DSI86  chip and got these errors. Also I found a strange problem, the 0x12  register can't be set to the correct value, since the display mode we use is 1080p, the value of 0x12 we have set it to 0x58 using the command:

i2cset -f -y 4 0x2c 0x12 0x58

But after set this register, we read it again, the value of this register was still 0x4c, and I don't know why？

We use imx8mp mipi dsi, the connection is as following:


The test script I used as following:
```

# ======REFCLK Frequency: Use DSI clk  ======

i2cset -f -y 4 0x2c 0x0A 0x03

# ======DSI Mode  ======

i2cset -f -y 4 0x2c 0x10 0x26

# =====DSIA Clock  ======

i2cset -f -y 4 0x2c 0x12 0x59

# =====DSIB Clock  ======

i2cset -f -y 4 0x2c 0x13 0x59

# ======DP Datarate  ======

i2cset -f -y 4 0x2c 0x94 0x20

# ======Enable PLL  ======

i2cset -f -y 4 0x2c 0x0D 0x01

# ======Enable ASSR in Panel  ======

i2cset -f -y 4 0x2c 0x64 0x01

i2ctransfer -f -y 4 w6@0x2c 0x74 0x00 0x01 0x0A 0x01 0x81

sleep 0.01

# ======Enable enhanced frame  in DSI86  ======

i2cset -f -y 4 0x2c 0x5A 0x04

# ======Number of DP lanes  ======

i2cset -f -y 4 0x2c 0x93 0x30

# ======Start Semi-Auto Link Training  ======

i2cset -f -y 4 0x2c 0x96 0x0A

sleep 0.02

# ======CHA Active Line Length  ======

i2cset -f -y 4 0x2c 0x20 0x0780 w

# ======CHB Active Line Length  ======

i2cset -f -y 4 0x2c 0x22 0x0000 w

# ======Vertical Active Size   ======

i2cset -f -y 4 0x2c 0x24 0x0438 w

# ======Horizontal Pulse Width   ======

i2cset -f -y 4 0x2c 0x2C 0x002C w

# ======Vertical Pulse Width   ======

i2cset -f -y 4 0x2c 0x30 0x0005 w

# ======HBP   ======

i2cset -f -y 4 0x2c 0x34 0x94

# ======VBP   ======

i2cset -f -y 4 0x2c 0x36 0x24

# ===== HFP  ======

i2cset -f -y 4 0x2c 0x38 0x58

# ===== VFP  ======

i2cset -f -y 4 0x2c 0x3A 0x04

# ===== DP-18BPP Disable  ======

i2cset -f -y 4 0x2c 0x5B 0x00

# ===== Color Bar Enable  ======

i2cset -f -y 4 0x2c 0x3C 0x13

# ===== Enhanced Frame, and Vstream Enable  ======

i2cset -f -y 4 0x2c 0x5A 0x0D

```

Also I saw a description in the datasheet:
In this example, the clock source for the SN65DSI86 is the REFCLK pin. When using the REFCLK as the clock source, any DSI Clock frequency is supported. But if the clock source was instead the DSI A clock, then the required DSI Clock frequency would need to change to a frequency supported by the SN65DSI86. When operating in this mode, any one of the following DSI A clock frequencies can be used: 384 MHz, 416 MHz, 460.8 MHz, 468 MHz, or 486 MHz. In most cases, a eDP panel would support some variation from the ideal pixel clock frequency.

Does this means if we don't use the refclk, the DSI clock must exactly match the options of: 384 MHz, 416 MHz, 460.8 MHz, 468 MHz, or 486 MHz?

Thank you very much!

Snow 

Best regards

Hi Snow, thank you for sharing the details about this. Please give me 2 days to check and get back to you.

Best regards,
Ikram

Hi Ikram

As we discussed before, we will use this bridge connect to the full DisplayPort monitor, But  as the datasheet described, this bridge is used for eDP, so is there will some issue when we use this bridge for full DisplayPort monitor?

Hi Snow,

To use this device with DP instead of eDP, please use the settings shared in this previous E2E: SN65DSI86: Using the Bridge as DSI to DisplayPort (not eDP)

Best regards,
Ikram

Hi Ikram

Thank you for you information, I saw there is SCRAMBLE_DISABLE bit in register 0x95, I want to know what is the relationship with the ASSR_CONTROL in register 0x5A?

If I set SCRAMBLE_DISABLE to 1, does that mean the bridge disables both the Standard DP Scrambler Seed and the Alternative Scrambler Seed Reset (ASSR)?

Hi Snow,

You can see on register 0x5A that there are options. Setting the bits 1:0 to 0 will select  Standard DP Scrambler Seed instead of ASSR. This is done because most DP monitors do not support ASSR.

If you do the register writes and hardware settings mentioned in the E2E thread, it should help to set up this device with DP configuration.

Best regards,
Ikram

Hi Ikram

Got it, I check the sn65dsi86 driver in https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/drivers/gpu/drm/bridge/ti-sn65dsi86.c
There are some codes related to the ASSR:

/*
	 * The SN65DSI86 only supports ASSR Display Authentication method and
	 * this method is enabled for eDP panels. An eDP panel must support this
	 * authentication method. We need to enable this method in the eDP panel
	 * at DisplayPort address 0x0010A prior to link training.
	 *
	 * As only ASSR is supported by SN65DSI86, for full DisplayPort displays
	 * we need to disable the scrambler.
	 */
	if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) {
		drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
				   DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);

		regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
				   SCRAMBLE_DISABLE, 0);
	} else {
		regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
				   SCRAMBLE_DISABLE, SCRAMBLE_DISABLE);
	}

I don't understand why it disable the SCRAMBLE for full DisplayPort displays, should not we use Standard DP Scrambler Seed for full DisplayPort display?

Best regards,
Ikram

Hi Snow,

Since the DSI86 only support ASSR, the scrambler should be disabled for using the DisplayPort displays.

Is there any issue you are facing with these settings?

Best regards,
Ikram

Hi Ikram

Yes, I found it is not stable when using this driver to test my DisplayPort monitor. 
I mean if we use DisplayPort, shouldn't we enable the scrambler, and set the bits 1:0 of 0x5A to 0, so that the bridge will select  Standard DP Scrambler Seed instead of ASSR. But the driver disable the scrambler, so that it will not select ASSR, and also not use  Standard DP Scrambler Seed, is this a correct solution?

Best regards,
Snow

Hi Snow,

In that case, you could try with 0x95 set for scrambling enabled and 0x5A set to Standard DP scrambler. Please let us know whether that corrects the issue.

With the scrambler not enabled, is there correct display or is there an issue such as flickering? When the issue occurs, please also check whether any errors are reported.

Best regards,
Ikram

Hi Ikram

Sorry for the late reply due to some busy business, We can't test DP mode because the hardware limit, we need to change the hardware layout to fix this.

BTW, there is a description in the datasheet:
ASSR_CONTROL.This field controls the scrambler seed used. Standard DP scrambler seed value is 0xFFFF. The ASSR seed value is 0xFFFF. This field is R/W if TEST2 pin is sampled high on rising edge of EN and bit 0 of offset 0x16 in Page 7 is set. Otherwise this field is readonly. 00 = Standard DP Scrambler Seed. 01 = Alternative Scrambler Seed Reset (Default). 10 = Reserved. 11 = Reserved.

Why the ASSR seed and  Standard DP scrambler seed value are the same value 0xFFFF?

Best regards,
Snow

Hi Snow, 

I will check this value for the scrambler seed and get back to you with an update by Tuesday.

Best regards,
Ikram