DS250DF230: CDR cannot be locked

Colin Chen

Part Number: DS250DF230

Dear experts

At present, the client is using SigCon Architect to test DS250DF230 and has found that CDR cannot be locked, as shown in the following figure.The input signal exists, and the signal input is a 25.78125Gbps optical module input

We have tested before that CDR can be locked with the same hardware and configuration, as shown in the following figure. At present, it is unclear what may affect this CDR lock, and I hope you can help investigate the cause,thank you

6 days ago

0 Drew Miller1 6 days ago

TI__Mastermind 37263 points

Hi Colin,

What is REFCLK frequency? The VCO count setting will depend on REFCLK frequency, but SigCon architect provide REFCLK frequency selection for this device.

Can you try referencing the "Register Settings for Common Data Rates using 25-MHz Calibration Clock" and "Register Settings for Common Data Rates using 30.72-MHz Calibration Clock (DS250DF230 Only)" tables in the programming guide and set 0x60-0x63 accordingly? These can be set via the low level page. Would recommend CDR reset after implementing these settings.

Thanks,

Drew

0 Colin Chen 3 days ago in reply to Drew Miller1

Intellectual 865 points

Hi Drew,

The REFCLK frequency is 25MHz. After checking the configuration of the 0x60-0x63 register, it is the same as the configuration provided in the programming guide; Here is the configuration we exported. Could you please help us check it if it's convenient? Thank you

ds250df230_config.cfg

0 Jianxiang Yang 1 day ago in reply to Colin Chen

Prodigy 20 points

Hi Drew,

I'm Colin's workmate, CDR lock issue seems sovled by fond one resistor around optical module damaged， after resolder this resistor, CDR can be locked.
but we find eye diagram on software seems not correct, please refer pictures attached.

which points we need to check for this issue? many thanks.

Interface

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DS250DF230: CDR cannot be locked