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DP83867IR: Fail at compliance test mode 4

Shota Mago
Expert 8480 points

Part Number: DP83867IR

Hi team,

My customer is struggling to pass test mode-4 of the compliance test of 1000BASE-T.

When they add disturbing signal and CLK_O_SEL is set to transmit clock, their board always fail the test. Wihout disturbing signal, it can pass the test successfully.

Is there anything to check?

They're asking another question about TXG_GAINSEL_FINE of 0x00A0 and 0x00A1. The datasheet states that gain can be increased up to +14% when the register is set to 0x1111. However, they see that amplitude got smaller than when it's set to 0x0000. They confirmed that the reigster as expected until 0x1110. Is there any limitation to use 0x1111 for TXG_GAINSEL_FINE?

 

Best regards,

Shota Mago

  • 0
    TI__Mastermind 22296 points

    Hi Mago-san,

    Is the customer failing the distortion test on the compliance test?

    Shota Mago said:
    They're asking another question about TXG_GAINSEL_FINE of 0x00A0 and 0x00A1. The datasheet states that gain can be increased up to +14% when the register is set to 0x1111. However, they see that amplitude got smaller than when it's set to 0x0000. They confirmed that the reigster as expected until 0x1110. Is there any limitation to use 0x1111 for TXG_GAINSEL_FINE?

    The A0 and A1 register is relative to the trim of the PHY, and the gains may not fully correlate to what is specified in the datasheet. Is the customer also seeing issue with the voltage template test?

    Best,
    J

  • 0 in reply to J
    TI__Expert 8480 points

    Hi J,

    J said:
    Is the customer failing the distortion test on the compliance test

    Yes.

    J said:
    The A0 and A1 register is relative to the trim of the PHY, and the gains may not fully correlate to what is specified in the datasheet. Is the customer also seeing issue with the voltage template test?

    The customer confirmed that the board can pass the template test with setting of Reg0x1D5 = F508. They just wanted to make sure function of A0 and A1 register. 

    Best regards,

    Shota Mago

  • 0 in reply to Shota Mago
    TI__Mastermind 22296 points

    Hi Mago-san, 

    On distortion, could the customer share the compliance report so we can see how badly it is failing?


    Shota Mago said:
    The customer confirmed that the board can pass the template test with setting of Reg0x1D5 = F508. They just wanted to make sure function of A0 and A1 register. 

    Their intuition is correct. A0 and A1 could give an additional gain amplitude if it is increased from the default trim value or vice versa. 

    Best,
    J

  • 0 in reply to J
    TI__Expert 8480 points

    Hi J,

    Sorry for late reply.

    I sent you the compliance report and test setup information through private message.

    Best regards,

    Shota Mago

  • 0 in reply to Shota Mago
    TI__Mastermind 22296 points

    Hi Mago-san, 

    Thank you for sending the message. I will respond on this post unless it involves the customer's setup in detail. 

    Best,
    J

  • 0 in reply to J
    TI__Mastermind 22296 points

    Hi Mago-san, 

    Thank you for the report. I have discussed this case internally and we have seen having a 10+nF capacitor on RBIAS mitigates distortion on our PHYs. I apologize that I cannot provide a solution that doesn't require a BOM change. 

    However, I would also like to note that the main goal of the distortion test is to check the accuracy of the 17 analog levels used in the 1000BASE-T transmitted signal. This test doesn't necessarily check for the signal integrity and the signal shape. Those are checked in the template test which ensures that the PHY outputs the correct voltage and signal shape that the receiver will be able to understand correctly. 

    Some of our PHYs may exceed IEEE 802.3-2008 distortion specification, but this will have no direct impact on system-level performance or interoperability. Its sole impact is to the IEEE conformance test result.

    Best,
    J