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TIOL221: SPI Daisy-Chaining TIOL221 devices

Part Number: TIOL221

Hello,

I'd like to know whether the TIOL221 devices support daisy-chaining for their SPI interface as described e.g. in https://www.ti.com/lit/pdf/slvae25 where

  • all devices share the SCLK and CSn signals
  • the SPI master's MOSI is connected to the SDI pin of the first TIOL221 device
  • the SDO pin of the (i)th TIOL221 device in the chain connects to the SDI pin of the (i+1)th TIOL221 device
  • the SDO pin of the last TIOL221 device in the chain connects to the SPI master's MISO pin.

Basically this comes down to the question whether for SPI shifts that are larger than the TIOL221's register size, the overflowing last bit re-appears on the SDO pin so it can be consumed by the next device in the chain.

I suppose daisy chaining might not be possible due to the burst read/write mode, but the data sheet does not really address whether there is a maximum burst length or whether burst mode is dependent on the chosen address or some modifier flag.

Thanks for your support.

  • Hi Christian,

    I'm sorry for the delay.  Unfortunately the TIOL221 does not support SPI Daisy-chaining.  Each TIOL221 must have it's own nCS signal because it returns the status register on the SDO line while the register address to read or write is input on the SDI pin.  This occurs for every Read and Write transaction as shown in the datasheet and is a way for the MCU to get the status register information more efficiently without having to perform a dedicated Read of the register.

    But as a result this prevents daisy-chaining the SPI because both the SDI and SDO pins are active for every SPI transaction.

    You can have the SCLK, SDI and SDO pins connected in parallel with other devices as long as the nCS signal is unique to the TIOL221 and it is not used for other devices at the same time on the same SPI bus.

    Regards,

    Jonathan