Part Number: TIOL221
Hello,
I'd like to know whether the TIOL221 devices support daisy-chaining for their SPI interface as described e.g. in https://www.ti.com/lit/pdf/slvae25 where
- all devices share the SCLK and CSn signals
- the SPI master's MOSI is connected to the SDI pin of the first TIOL221 device
- the SDO pin of the (i)th TIOL221 device in the chain connects to the SDI pin of the (i+1)th TIOL221 device
- the SDO pin of the last TIOL221 device in the chain connects to the SPI master's MISO pin.
Basically this comes down to the question whether for SPI shifts that are larger than the TIOL221's register size, the overflowing last bit re-appears on the SDO pin so it can be consumed by the next device in the chain.
I suppose daisy chaining might not be possible due to the burst read/write mode, but the data sheet does not really address whether there is a maximum burst length or whether burst mode is dependent on the chosen address or some modifier flag.
Thanks for your support.