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DS160PT801: Is there an algorithm to override DFE and Ref0,Ref1

Tony Zabinski
Prodigy 110 points

Part Number: DS160PT801

Hi,

 

   We are debugging a low temperature(near -40C) failure.   Seems to be downstream receivers.

We can see one lane margin dithering over time from good to small.  We do not believe the transmitter is varying - Only the retimer end is at low temperature.

I do realize in general the guidance is that auto tuned is best.  Just trying to nail down the failure by over-riding.

We ar efinding that the FSM seems to keep adjusting...

      Refs end up -64,+64 and DFE tap1 moves to the extreme.   And if we apply the overrides before link training, it links gen1, but doesn't seem to attmept to advance to next speeds.

We are setting:   Ov_en and value in 0xC3, Value in C4, ov_en and value in C5,C6

   Tried also: Reg 0x58:  The suggested EEPROM file value, as well as masking DFE

   Also, reg 0xB6, all combinations of bits 2 and 3


Any advice is appreciated.

   

    

 

 

  • 0
    TI__Expert 8760 points

    Hi Tony,

    I will look into this and get back to you as soon as possible.

    Best regards,

    Greg

  • 0
    TI__Expert 8760 points

    Hi Tony, 

    Apologies for the delay. Are you seeing the same results when overriding in normal temperature conditions? Generally, the DFE override is not recommended for most applications. I will check with our design team to see if the override requires further configuration or if it is not as effective in low temperature.

    Best regards,

    Greg

  • 0
    Prodigy 110 points

    Hi Greg,   I think my settings have two problems:

    Does not seem to stop DFE/VREF auto cal.  It always adjusts to extremes when I override, regardless of temperature.

    Second problem, it seems like I missed a mechanism so the Link Training can progress with DFE overridden.    I can override when already at Gen4, linked, and it remains linked.  If I override before Link training, it never attempts speed jump - Just remains Gen1.

    I'd say don't spend time on this, but if someone that worked with this part in the lab has register settings that work, I'd give them a try.     We are spinning our designs for this topology to have another retimer(fewer connectors between),  to hopefully alleviate the problem.

    What about settings that might affect DFE/Ref and maybe CDR:

       We believe our problem is asymmetric RX eye 'fooling' the sampler off the edge of the eye.     We start with around .6UI, 160mV eye, but over time and temperature see it decrease, then return. One lane in particular( package pins P3, N4), but all lanes on this interface drift a little.   The only control we have on the incoming RX is the preset we send to the host...

       Wondering if there are settings that could limit how fast DFE and CDR can adjust?   We do not support Spread_Spectrum, so I think if we could ensure all training FSMs take longer, it would statistically avoid whatever is making it drift.

    Thanks,
    Tony

  • 0 in reply to Tony Zabinski
    TI__Expert 8760 points

    Hi Tony,

    I can reach out to the testing group to find if anyone has worked with similar testing and ran into CDR not locking/eye issues under lower temperatures.

    Best regards,

    Greg

  • 0 in reply to Gregory Kobyakov
    TI__Expert 8760 points

    Hi Tony,

    If you add me back as a friend on E2E, I can share some scripts to check the DFE override. Our team would prefer sharing this over private message.

    Best regards,

    Greg

  • 0 in reply to Gregory Kobyakov
    Prodigy 110 points

    Hi Greg - I added you as a friend.


    Tony

  • 0 in reply to Tony Zabinski
    TI__Expert 8760 points

    Hi Tony,

    Just responded, thank you.

    Best regards,

    Greg