DS92LV16 Timing Clarifications

Vini

Other Parts Discussed in Thread: DS92LV16

Hi,

I have a doubt regarding the timing details in DS92LV16. As per datasheet, setup and hold times are given as shown below

Now as per these specs, min hold time 0.35*clock period.

Now considering this worst case scenario, when I consider hold time as 0.35*clock period, what will be the max setup time for data during next cycle?

Values for max setup and hold time are not given in datasheet. So, should I consider max setup time as (1-0.35)*clock period i.e. 0.65*clock period or only 0.5*clock period?

If I take it as 0.65*clock period, it means data will change before next falling edge as setup time is more than half a clock cycle. Is my understanding correct here?

Taking min hold time as 0.35*clock period and if max setup time is 0.5*clock period only, then what data will be there, what data will be there for remaining 0.15*clock period? Will it be high imedance?

Regards,

Vinod

over 13 years ago

0 John Goldie over 13 years ago

TI__Expert 5175 points

Greetings -

This parameter is really defining the Data Valid before Clock (SET) and Data Valid after Clock (Hold) times for the DES output.

Lets assume the clock is perfect in the middle of the data bit, and with ideal edges, the largest SET time would be 0.5 of the clock period. And likewise, the ideal hold is also 0.5 of the clock period. (SET plus HOLD <= clock period)

Now to take into clock edge placement, skew, and transition times, this part's datasheet indicates it will be at least 0.35 of the clock period for both parameters. The parameter is also defined as DATA-to-CLOCK, thus the HOLD time is a negative, the clock edge occurs before the data edge for the next bit - thus negative.

Lets plug in some numbers, at 80MHz, the clock period is 12.5ns. The Data is Valid at least 4.375ns before the clock edge, and the HOLD is valid for at least another 4.375ns. In this case the data is Valid for 70% of the clock period. Only the MIN value is of importance.

Best Regards;

John Goldie
DPS APPS / SVA / www.ti.com

0 Vini over 13 years ago in reply to John Goldie

Intellectual 895 points

Hi John,

I understand that usually minimum values only matters for setup and hold time. But I am actually more concerned about maximum values for these parameters.

In my case, I have a complex digital logic after de-serializer and these timings have become very important for me. Basically, it is a stereo camera logic and I am sampling data twice in one RCLK cycle (using an RCLK x 2 clock). I also have a logic to extract SYNC information from this data which is embedded into the data by sensor and based on this timing I need extra logic to avoid any false edges on my SYNC signals.

My main doubt is can setup/hold time be more than 0.5 * RCLK?

As shown in the below diagram, Data1 sample is valid for 13.46ns after RCLK rising edge (for a 26MHz RCLK). Now setup time for Data2 sample becomes 0.65*RCLK which is greater than 0.5*RCLK.

I understand the factors taken into account for giving these timings but just wanted to clarify whether data can change before next falling edge of RCLK (i.e. in the region marked as yellow in below diagram)?

Minimum setup and hold time are understood but what can be the worst case max setup/hold time?

2620.Visio-SERDES.pdf

Vini

0 John Goldie over 13 years ago in reply to Vini

TI__Expert 5175 points

Greetings -

Please note the DES output is really defining the DATA VALID BEFORE CLOCK EDGE and also DATA VALID AFTER CLOCK EDGE. We state a MIN and a TYP. The TYP is the one that matters as DATA WILL NOT CHANGE in this windown around the RISING clock edge.

In your 26 MHz example, the clock period is 38.46ns.

DATA will be stable for atleast 35% of the clock period or 13.46ns BEFORE the clock RISE edge, AND

DATA will be stable for atleast 35% of the clock period or 13.46ns AFTER the clock RISE edge.

The DES provided the 1X clock out and the data valid is assured around that edge. If you externally generate a 2X clock, it is up to you to manage the phase and results data Valid times to meet the down stream input requirments for set and hold. The DES can only specify and reference to its output clock. See FIG 11 for the DES output timing in the datasheet.

John Goldie

DPS APPS / SVA / www.ti.com

0 Vini over 13 years ago in reply to John Goldie

Intellectual 895 points

Hi John,

I understand that MIN is that matters and is guaranteed around the rising clock edge.

I was just curious to know whether data can really change before falling edge of clock. In theory, if data is output by DES w.r.t. falling edge, then it cannot change before that edge. But practically clock edge can come before or later than data due to skew etc. and especially it can happen more if data is output by DES w.r.t. some internal higher clock and not w.r.t. actual RCLK output.

Anyway, I have done a thorough timing analysis with 2X clock I am using with MIN timing parameters and I have enough margins, at least in theory. I have tested a part of it with the eval kit and it is working correctly.

Thanks a lot for your support.

Regards,

Vini

0 John Goldie over 13 years ago in reply to Vini

TI__Expert 5175 points

Hi Vini -

Glad to hear you have been able to prototype this and are able to observe the resulting timing and ensure it meets your special downstream requirments.

John

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DS92LV16 Timing Clarifications