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DP83867IR: DP83867IRRGZR on Intel Amston Lake Platform – BIOS Integration and MAC Address Programming

JIM SHEN
Prodigy 90 points

Part Number: DP83867IR


Hello,

I’m using the DP83867IRRGZR PHY on an Intel platform, and I would like to confirm a few points:

  1. Does the BIOS need to include any specific driver, firmware, or initialization code for this PHY?

  2. What is the recommended method to program or assign the MAC address in this setup?

Thank you for your support and clarification.

Best regards,
jim

  • +1
    TI__Mastermind 26791 points

    Hi Jim, 

    The PHY needs driver. We provide Linux driver for DP83867. Our driver does not handle the MAC addressing. However, we do support keeping track of MAC addresses for WoL purposes. For MAC addresses, please refer to the SoC's guideline.

    Best,
    J

  • 0 in reply to J
    Prodigy 90 points

    HI J

    Intel advised us to contact TI regarding the "TI LAN bin file" for DP83867IRRGZR. Could you please clarify:

    1) Do you provide any vendor .bin or firmware file for DP83867IRRGZR? If yes, what is the purpose (e.g., PHY NVM image, special register patches, WoL table, TSN-related settings)?

    2) For an Intel TwinLake platform using DP83867 connected to HSIO6, is it required to place any TI-provided .bin into Intel ME GBE region? If not, what is the recommended mechanism to load/apply this bin (e.g., write to PHY NVM via production programming, load by OS driver at runtime, or place in board EEPROM)?

    3) Any recommended PHY register settings or strap defaults for interoperability with Intel MAC (RGMII timing/clock recommendations)?

    Best regards,
    jim

  • 0 in reply to JIM SHEN
    TI__Mastermind 26791 points

    Hi Jim, 

    We only have Linux driver for DP83867. This driver is used to initialize the PHY HW configuration and loads our PHY into Linux OS. It also handles WoL, but there is no special register patches unless you add them in. 
    You can find the driver file via this link:https://www.ti.com/tool/ETHERNET-SW

    Most of our customers load the driver using OS at the bootup. 

    We have no guideline for RGMII timing, but there can be timing mismatches so if the PHY has a link up but the Intel MAC is not receiving any data, I would suggest to shift RGMII TX timing using the Intel MAC and RGMII RX timing using the PHY. The PHY supports up to 4ns of clock delay and can be shifted 250ps. In addition, the default on the RGMII shift mode on the PHY is 2ns. 

    Best,
    J