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SN75LVPE5412: Question about SN75LVPE5412

Jimmy Huang
Genius 3985 points

Part Number: SN75LVPE5412

Hello:

PN#SN75LVPE5412RUAT
1. Can two SN75LVPE5412 be connected in series from RC to EP for PCIe Gen5 applications?
2. For a link from RC to EP, if half of the lanes have SN75LVPE5412 strung on them and half of the lanes do not, is there a problem with this application?
3. Regarding the protocol, is the chip SN75LVPE5412 transparent?

Thanks!!!

  • 0
    TI__Mastermind 26771 points

    Hi Jimmy,

    1. We do not recommend to cascade redrivers in series.

    2. If some links have redrivers and others do not, there may be an interpair skew issue. However, PCIe is more forgiving on this and upto 1 in trace difference should not cause an issue.

    3. This device has RX detect state machine as defined by PCIe specification but is protocol transparent otherwise.

    Best,

    J

  • 0 in reply to J
    Prodigy 70 points

    Hi J,

    Thank you for your reply.

    Could u help to continue checking the following questions?

    1a, May I know what's the concern here of rederivers in series application?

    1b, Is there any retimer based MUX from TI?

    1c, Does this "SN75LVPE5412RUAT" support aurora interface from AMD/Xillinx FPGA?

    Many thanks!

    Best regards,

    Anita Wei

  • 0 in reply to Anita Wei
    TI__Mastermind 26771 points

    Hi Anita,

    Redrivers do not clean up other jitter besides ISI jitter so cascading redrivers will add other jitter up.

    Unfortunately, we do not have retimer solution and this device should be supported by AMD FPGA as this device is protocol agnostic.

    Best,

    J