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SN65DSI83: SN65DSI83 TEST

hailei yang
Prodigy 20 points
Part Number: SN65DSI83


I am currently debugging MIPI to LVDS. First, I need to confirm whether the hardware is working properly. I can configure SN65DSI83 via I2C. I tried using the tunner tool to generate sequences, but the test pattern still doesn't display on the screen. It seems the clock is not aligned. I found a 24M clock that can be connected to the chip. May I ask how to configure the tunner? I have attached the schematic diagram and screen parameters.
Are there any precautions for controlling the enable pin of the chip?
image.png

image.png
 
image.png
  • 0
    TI__Mastermind 26380 points

    Hi Hailei,

    For the EN pin, please check the datasheet initialization sequence the EN pin control. It describes when the EN pin should be set.

    For using the REFCLK, there is an option in the DSI Tuner GUI to change clock source from DSI clock to REFCLK. And you can set the multiplier so that the LVDS clock output is a multiple of the REFCLK. 

    For example if the REFRCLK = 24 MHz, and the multiplier is set to 2, then the resulting output LVDS clock would  be 48 MHz.


    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    Prodigy 20 points

    Thanks, 

    You can take a look at our schematic diagram. We have a 2-lane MIPI that converts to 4-lane LVDS.
    I have another question. Our MIPI has 2 lanes, and the target LVDS for conversion needs to have 4 lanes. Is that okay? ​
    I'm worried that a 2-lane MIPI can only convert to a 2-lane LVDS.
  • 0 in reply to hailei yang
    TI__Mastermind 26380 points

    Hi Hailei,


    hailei yang said:
    Our MIPI has 2 lanes, and the target LVDS for conversion needs to have 4 lanes. Is that okay?

    Yes this should be okay. The LVDS output will be 3 or 4 lane, depending on the bits per pixel (color depth). And the input vary in number of DSI lanes used.

    However, note that the device will have to be programmed based on number of DSI lanes used, and resulting DSI clock rate for that resolution.

    Please let us know if you have further questions, or any queries about using the DSI Tuner tool.

    Best regards,
    Ikram

  • 0 in reply to Ikram Haque
    Prodigy 20 points
    I used a 32M reference clock and generated some configurations through a tunner, which enabled the display of images. However, there are some noise points in the images. ​
    1. Where is the anomaly? Are there any guidelines? ​
    1. The data sheet seems to be inconsistent. The tool requires writing 0x36 to register 0x10, but bits 1 and 2 are not described in the data sheet.
    echo 108 > /sys/class/gpio/export
    echo out > /sys/class/gpio/gpio108/direction
    echo 1 > /sys/class/gpio/gpio108/value

    i2cset -y 1 0x2c 0x09 0x01
    i2cget -y 1 0x2c 0x09
    i2cset -y 1 0x2c 0x09 0x00
    i2cset -y 1 0x2c 0x0A 0x00
    i2cset -y 1 0x2c 0x0B 0x00
    i2cset -y 1 0x2c 0x0D 0x00
    i2cset -y 1 0x2c 0x10 0x36
    i2cset -y 1 0x2c 0x11 0x00
    i2cset -y 1 0x2c 0x12 0x26
    i2cset -y 1 0x2c 0x13 0x00
    i2cset -y 1 0x2c 0x18 0x76
    i2cset -y 1 0x2c 0x19 0x00
    i2cset -y 1 0x2c 0x1A 0x03
    i2cset -y 1 0x2c 0x1B 0x00
    i2cset -y 1 0x2c 0x20 0x20
    i2cset -y 1 0x2c 0x21 0x03
    i2cset -y 1 0x2c 0x22 0x00
    i2cset -y 1 0x2c 0x23 0x00
    i2cset -y 1 0x2c 0x24 0x00
    i2cset -y 1 0x2c 0x25 0x00
    i2cset -y 1 0x2c 0x26 0x00
    i2cset -y 1 0x2c 0x27 0x00
    i2cset -y 1 0x2c 0x28 0x20
    i2cset -y 1 0x2c 0x29 0x00
    i2cset -y 1 0x2c 0x2A 0x00
    i2cset -y 1 0x2c 0x2B 0x00
    i2cset -y 1 0x2c 0x2C 0x14
    i2cset -y 1 0x2c 0x2D 0x00
    i2cset -y 1 0x2c 0x2E 0x00
    i2cset -y 1 0x2c 0x2F 0x00
    i2cset -y 1 0x2c 0x30 0x0a
    i2cset -y 1 0x2c 0x31 0x00
    i2cset -y 1 0x2c 0x32 0x00
    i2cset -y 1 0x2c 0x33 0x00
    i2cset -y 1 0x2c 0x34 0x2e
    i2cset -y 1 0x2c 0x35 0x00
    i2cset -y 1 0x2c 0x36 0x00
    i2cset -y 1 0x2c 0x37 0x00
    i2cset -y 1 0x2c 0x38 0x00
    i2cset -y 1 0x2c 0x39 0x00
    i2cset -y 1 0x2c 0x3A 0x00
    i2cset -y 1 0x2c 0x3B 0x00
    i2cset -y 1 0x2c 0x3C 0x00
    i2cset -y 1 0x2c 0x3D 0x00
    i2cset -y 1 0x2c 0x3E 0x00
    i2cset -y 1 0x2C 0x0D 0x01
    i2cset -y 1 0x2C 0x09 0x01
    i2cset -y 1 0x2C 0xE5 0xFF



  • 0 in reply to hailei yang
    TI__Guru** 113050 points

    Hello,

    The team is out due to a public Holiday in the US. Responses will be delayed until Monday.

    Thank you for your patience

  • 0 in reply to Hamzeh Jaradat
    TI__Mastermind 26380 points

    Hi Hailei,

    hailei yang said:
    The data sheet seems to be inconsistent. The tool requires writing 0x36 to register 0x10, but bits 1 and 2 are not described in the data sheet.

    These bits are ignored here since they are only used for channel B, which is not applicable here. This should be okay.

    Did you try using the test pattern? Please program with test pattern enabled and check if the timings are okay.

    It's possible that the REFCLK frequency and the DSI video data lanes do not match frequency exact causing this issue. What DSI clock frequency is the DSI source set to? Is it for precisely 32 MHz LVDS clock output as well?

    Best regards,
    Ikram