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DP83867IR: Simulation results

Part Number: DP83867IR

Hi,

I have ran the simulation for DP83867IR, TX lines and attached the results of the same. Kindly validate the reaults and let me know if this all can be considered as passed. I have a slight ring back on VIL with case1, the case1 is with addition of C_Comp caps of 4.8pF added near the PHY. Is this ring back on VIL is acceptable?

Thanks,

Usman

 AM64_ANI_LVCMOS_CPSW_RGMII1_Fast_1P8_IO.pdf 

  • Hi Usman,

    As previously discussed, as long as the ringback does not violate Vcc/2 and meet setup/hold time from Vcc/2, it will meet the PHY’s RGMII standards. Rise and fall time do not matter much for the PHY.

    Best,
    J