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SN65DSI83: Issue with SN65DSI83 LVDS Test Pattern Not Displaying on Panel

Hanwei Ke
Prodigy 10 points
Part Number: SN65DSI83


Hello,

We are testing the SN65DSI83 MIPI DSI to LVDS bridge with a display (datasheet attached). The converter is connected to an SC200E module running Android 14. We have a custom driver that writes the I²C registers to the SN65DSI83.

To validate the connection between the display and the converter, we configured the device to output the LVDS test pattern. However, we do not see any pattern on the screen.

We are attaching:


Additional details:

  • We tried changing register 0x1A to value 0x01 (100ohm differential termination), but the issue persists.
  • I think the driver logs look correct and indicate that the I2C writes are successful:
    bengal:/ # dmesg -w | grep convert
[    5.194323] convert_probe, Start
[    5.199539] mipi_convert 0-002c: convert_parse_dt: Pincontrol DT property failed
[    5.247071] mipi_convert 0-002c: 0-002c supply avdd not found, using dummy regulator
[    5.254936] mipi_convert 0-002c: Linked as a consumer to regulator.0
[    5.261317] mipi_convert 0-002c: convert IC probe success
[    5.266741] mipi_convert 0-002c: init convert IC ...
[    6.344369] mipi_convert 0-002c: reg: 9, READ8: 0
[    6.344609] mipi_convert 0-002c: reg: a, READ8: 85
[    6.344848] mipi_convert 0-002c: reg: b, READ8: 10
[    6.345085] mipi_convert 0-002c: reg: d, READ8: 1
[    6.345323] mipi_convert 0-002c: reg: 10, READ8: 26
[    6.345561] mipi_convert 0-002c: reg: 11, READ8: 0
[    6.345800] mipi_convert 0-002c: reg: 12, READ8: 2a
[    6.346039] mipi_convert 0-002c: reg: 13, READ8: 0
[    6.346276] mipi_convert 0-002c: reg: 18, READ8: 78
[    6.346514] mipi_convert 0-002c: reg: 19, READ8: 0
[    6.346752] mipi_convert 0-002c: reg: 1a, READ8: 1
[    6.346989] mipi_convert 0-002c: reg: 1b, READ8: 0
[    6.347227] mipi_convert 0-002c: reg: 20, READ8: 0
[    6.347465] mipi_convert 0-002c: reg: 21, READ8: 5
[    6.347702] mipi_convert 0-002c: reg: 22, READ8: 0
[    6.347940] mipi_convert 0-002c: reg: 23, READ8: 0
[    6.348181] mipi_convert 0-002c: reg: 24, READ8: 20
[    6.348420] mipi_convert 0-002c: reg: 25, READ8: 3
[    6.348659] mipi_convert 0-002c: reg: 26, READ8: 0
[    6.348896] mipi_convert 0-002c: reg: 27, READ8: 0
[    6.349135] mipi_convert 0-002c: reg: 28, READ8: 21
[    6.349372] mipi_convert 0-002c: reg: 29, READ8: 0
[    6.349612] mipi_convert 0-002c: reg: 2a, READ8: 0
[    6.349850] mipi_convert 0-002c: reg: 2b, READ8: 0
[    6.350088] mipi_convert 0-002c: reg: 2c, READ8: 50
[    6.350326] mipi_convert 0-002c: reg: 2d, READ8: 0
[    6.350563] mipi_convert 0-002c: reg: 2e, READ8: 0
[    6.350801] mipi_convert 0-002c: reg: 2f, READ8: 0
[    6.351039] mipi_convert 0-002c: reg: 30, READ8: a
[    6.351276] mipi_convert 0-002c: reg: 31, READ8: 0
[    6.351515] mipi_convert 0-002c: reg: 32, READ8: 0
[    6.351752] mipi_convert 0-002c: reg: 33, READ8: 0
[    6.351991] mipi_convert 0-002c: reg: 34, READ8: 28
[    6.352231] mipi_convert 0-002c: reg: 35, READ8: 0
[    6.352469] mipi_convert 0-002c: reg: 36, READ8: 14
[    6.352707] mipi_convert 0-002c: reg: 37, READ8: 0
[    6.352945] mipi_convert 0-002c: reg: 38, READ8: 28
[    6.353183] mipi_convert 0-002c: reg: 39, READ8: 0
[    6.353421] mipi_convert 0-002c: reg: 3a, READ8: a
[    6.353658] mipi_convert 0-002c: reg: 3b, READ8: 0
[    6.353896] mipi_convert 0-002c: reg: 3c, READ8: 10
[    6.354135] mipi_convert 0-002c: reg: 3d, READ8: 0
[    6.354372] mipi_convert 0-002c: reg: 3e, READ8: 0
[    6.354610] mipi_convert 0-002c: reg: d, READ8: 1
[    6.372320] mipi_convert 0-002c: reg: 9, READ8: 0
[    6.392082] mipi_convert 0-002c: End of convert_init
[    8.424484] mipi_convert 0-002c: reg: e5, READ8: 25
[   10.440492] mipi_convert 0-002c: reg: e5, READ8: 0
[   12.456496] mipi_convert 0-002c: reg: e5, READ8: 0
[   14.479241] mipi_convert 0-002c: reg: e5, READ8: 0
[   16.531441] mipi_convert 0-002c: reg: e5, READ8: 0
[   18.600477] mipi_convert 0-002c: reg: e5, READ8: 0
[   20.616473] mipi_convert 0-002c: reg: e5, READ8: 0
[   22.632504] mipi_convert 0-002c: reg: e5, READ8: 0
[   24.648499] mipi_convert 0-002c: reg: e5, READ8: 0
[   26.664560] mipi_convert 0-002c: reg: e5, READ8: 0
[   28.681645] mipi_convert 0-002c: reg: e5, READ8: 0
[   30.697030] mipi_convert 0-002c: reg: e5, READ8: 0
[   32.713776] mipi_convert 0-002c: reg: e5, READ8: 0
[   34.728522] mipi_convert 0-002c: reg: e5, READ8: 0
[   36.744504] mipi_convert 0-002c: reg: e5, READ8: 0
[   38.760907] mipi_convert 0-002c: reg: e5, READ8: 0
[   40.776600] mipi_convert 0-002c: reg: e5, READ8: 0
[   42.792595] mipi_convert 0-002c: reg: e5, READ8: 0
[   44.810617] mipi_convert 0-002c: reg: e5, READ8: 0
[   46.824672] mipi_convert 0-002c: reg: e5, READ8: 0
[   48.844633] mipi_convert 0-002c: reg: e5, READ8: 0
[   50.856620] mipi_convert 0-002c: reg: e5, READ8: 0
[   52.875207] mipi_convert 0-002c: reg: e5, READ8: 0
[   54.888890] mipi_convert 0-002c: reg: e5, READ8: 0
[   56.905806] mipi_convert 0-002c: reg: e5, READ8: 0
[   58.920638] mipi_convert 0-002c: reg: e5, READ8: 0
[   60.936559] mipi_convert 0-002c: reg: e5, READ8: 0
...

     

Could you please help us identify why the test pattern is not appearing? 

Thank you for your support.
Hanwei

  • 0
    TI__Mastermind 36245 points

    Hi Hanwei,

    Thank you for providing the display datasheet, DSI tuner output, and DSI83 register dump.

    The typical LVDS clock of the display is 71.11MHz. For non-burst DSI with 4 lanes, the DSI frequency is 213.3MHz which I see is already divided by 3 in the DSI83 to output the LVDS clock. Can you confirm that this DSI frequency is output by the SC200E module?

    Has the DSI83 already been tested with the normal DSI input?

    Best,

    Jack

  • 0 in reply to Jack Scherlag
    Prodigy 10 points

    Hi Jack,

    I reviewed the clocks, and it seems the DSI output is 72 MHz according to the logs I captured:

    bengal:/sys/kernel/debug/clk # cat dsi
dsi0_phy_pll_out_byteclk/           dsi0pll_n2_div_clk/                 dsi0pll_shadow_byte_clk_src/        dsi0pll_shadow_post_n1_div_clk/
dsi0_phy_pll_out_dsiclk/            dsi0pll_pixel_clk_src/              dsi0pll_shadow_n2_div_clk/          dsi0pll_shadow_vco_clk_14nm/
dsi0pll_byte_clk_src/               dsi0pll_post_n1_div_clk/            dsi0pll_shadow_pixel_clk_src/       dsi0pll_vco_clk_14nm/
bengal:/sys/kernel/debug/clk # cat dsi0_phy_pll_out_byteclk/clk_rate
54432000
bengal:/sys/kernel/debug/clk # cat dsi0_phy_pll_out_dsiclk/clk_rate
72576000
bengal:/sys/kernel/debug/clk # cat dsi0pll_pixel_clk_src/clk_rate
72576000

    If by “normal DSI input” you mean writing the registers without enabling the test pattern in DSI Tuner, we haven’t tested that yet. However, in theory, the behavior shouldn’t improve compared to test mode, right? Our first goal is to ensure first the connection between the display and the converter is correct.

    As additional information, I’m attaching the .dsi file I used to calculate the registers. When importing a file in DSI Tuner, the test pattern option is never checked by default, so I’m sending you the normal mode .dsi. To get the same register values as in the driver, you just need to enable the test pattern option.

    If the DSI clock is 72 MHz, I understand we don’t need to apply any divider, correct? Could this be the reason why we’re not seeing anything on the display?

    Best regards,
    Hanwei

  • 0 in reply to Hanwei Ke
    Prodigy 10 points

    I think I can’t upload .dsi format files on this platform, but the register dump I already shared should be enough for you to review.

    Please let me know if you need any additional details.

  • 0 in reply to Hanwei Ke
    TI__Mastermind 36245 points

    Hi Hanwei,

    Hanwei Ke said:
    If the DSI clock is 72 MHz, I understand we don’t need to apply any divider, correct? Could this be the reason why we’re not seeing anything on the display?

    The DSI clock is too low for the video timings supported by the display. The required video bit rate can be calculated by multiplying PCLK by the pixel depth

    71.11MHz * 24bits per pixel = 1.706Gbps

    This video bit rate needs to be supported across all 4 DSI lanes. We can use the following equation to calculate required DSI clock. DSI clock frequency = Video bit rate / (Num of DSI lanes * 2)

    This gives us a DSI clock frequency of 213.3MHz. Try using this DSI clock frequency.

    Best,

    Jack