Hi team,
I am considering a circuit that controls the EN signal after the VREF1 and VREF2 power supplies are turned on.
Can the EN signal be either push-pull or open-drain?
I am considering using a dual-supply buffer (push-pull) to control the EN signal.
Also, is it possible to add a pull-down resistor to the EN signal?
Sincerely,
Hi Higuchi-san,
I am not sure of your complete implementation with the voltage levels for your application, but if you are using a push-pull signal for the VREF2 supply, this would be okay.
I used 3.3V signal as an example. Either the pin is controlled to 3.3V or 0V.
Note that VREF2+EN = VREF1 + VTH, where the threshold voltage is estimated to be 0.6 V.
I am considering using a dual-supply buffer (push-pull) to control the EN signal.
Also, is it possible to add a pull-down resistor to the EN signal?
If you are planning on using a push-pull signal to control the EN directly, this implementation would not work.
Because now you are setting the VREF2+EN = 3.3V or 0V by the push-pull circuit. This affects the gate bias on the channel FET connecting SCL1 -- SCL2 and SDA1 --SDA2. The push-pull circuit will set the voltage at EN too HIGH.
If you have a pull-down resistor to the EN signal, this will create a voltage divider with the 200kohm resistor, and the device will always be OFF unless driven HIGH.
Please confirm your voltage requirements for this application so I can best assist. Also are you using level translation mode or switch mode?
Regards,
Tyler
Thank you for your response.
The voltage requirements are as follows:
VREF1: VADJ (1.2V to 3.3V)
VREF2: 3.3V
Since VREF1 may equal VREF2, we are considering a switch mode solution.
We are sending the configuration currently under consideration.
Sincerely,
Higuchi-san,
This implementation will not work properly.
When VADJ = 1.2V and side 2 is pulled up to 3.3 V, the device will create a voltage divider from the 3.3V supply through 2k PU resistor through the channel FET through the 2k PU resistor into the 1.2 V supply.
I recommend shorting the EN+VREF2 connection after the 200k resistor. This is proper use-case of the PCA9306:
What is the purpose of the TXU0101?
When A = HIGH, the output is pulled down to GND by a 10k PD resistor. The PCA9306 will always be OFF in this case.
Regards,
Tyler
Hi team,
Thank you for your answer.
You gave an example where VREF1 = 1.2V, but will it also work when VADJ = 1.2V, 1.8V, or 3.3V?
The TXU0101 is used to monitor whether both power supplies are ON.
I expect EN = HIGH when both power supplies (VCCA, VCCB) are ON.
The power-on timing for VADJ and +3.3V depends on the opposing board,
so I would like the circuit to enable EN after both power supplies are ON.
I have revised the circuit configuration.
Will this configuration be possible?
Sincerely,
Hi Higuchi-san,
I see what you are trying to do in the original implementation of the 10k PD resistor. When VADJ = 0V, the TXU0101 is OFF, so BY output floats. A 10k PD resistor is used to bias appropriately, so that EN = ~ 0V and the PCA9306 is in HIGH-Z. However, when the TXU0101 will output a logic HIGH on BY. With the 10k PD resistor, this will sink an IOH from the TXU0101 of about 3.3V / 10k = 0.33 mA . I suspect there to be some voltage drop at the output at BY, maybe instead of 3.3V VOH, the voltage is 3.2V. Regardless, Since the PCA9306 is setup in level translation mode with EN+VREF2 shorted together, this will adjust the EN voltage to a VADJ + VTH = VADJ + 0.6V and allow proper level translation to the 3.3V side for all three cases of VADJ = 1.2V / 1.8 V / 3.3V.
This would be a valid use case:
Regards,
Tyler
Hi team,
Thank you for your answer.
Would it be possible to operate at VADJ=3.3V with the proposed design?
Best regards,
